# 1-M2 - Midterm 2 ECE 25, Fall 2010 Tuesday, November 23,...

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Consider the following sequential logic diagram where I is an external input . Assume the gate delay is 2ns for a 2-AND gate and 3ns for a 2-XOR gate. Assume the positive edge-trigged ﬂip-ﬂop delay is T delay FF = 1ns , and setup time is also T setupFF = . What is the minimum clock period that would satisfy these delays? Provide the critical path. Clock period = Critical path = D-FF XOR AND D-FF AND AB CD D-FF AND E G AND F H I 1

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2) Sequential logic implementation (10 pts) Consider the following Moore machine with initial state A . (“*” means don’t care.) S 1 + S 0 + S 1 S 0 JK =00 =01 =10 =11 F A ABCA 1 B BAAC * C CBBA 1 Assume the following state encoding. State S 1 S 0 A 00 B 11 C 10 Fill-out the following K-Maps. 00 01 11 10 JK S1+ 00 01 S1S0 11 10 00 01 11 10 JK S0+ 00 01 S1S0 10 01 S0 F 0 1 S1 2
3) Timing analysis (10 pts) Consider the following sequential logic diagram. Assume the gate delays are 1ns for XOR gates and INVERTERS. Assume the positive edge-trigged ﬂip-ﬂop delay is T delay FF = , and setup time is also T setupFF = .

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## This note was uploaded on 01/09/2012 for the course CSE 140 taught by Professor Rosing during the Spring '06 term at UCSD.

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1-M2 - Midterm 2 ECE 25, Fall 2010 Tuesday, November 23,...

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