2-F - 1 Two-level logic minimization(10 pts Consider the...

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1) Two-level logic minimization (10 pts) Consider the logic diagram shown below. A B C OR F 0 1 0 1 0 1 B D B C D a) Please fill out the following K-map for F as a function of A , B , C , and D . 00 01 11 10 CD F 00 01 AB 11 10 b) For the K-map derived in part (a) for F , specify all the primes and essential primes. Prime Essential c) Find the minimum two-level logic implementation for F . F = 2
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2) Number representation (10 pts) a) For each binary vector below, what does it represent as an Octal number and a Hexadecimal number? Binary Octal Hexadecimal 00111110 10100001 00111001 b) Given X and Y below that are 5-bit numbers in 2’s complement form, fill in the table of what S should be bit-vector form ( even if the result causes an overflow ). Indicate whether or not there is an overflow and what S is as a number (if S results in an overflow, then just put an ”x” under the “ S as a number” column). (First two rows provide examples.) X Y S = X Y S as a x 4 x 3 x 2 x 1 x 0 y 4 y 3 y 2 y 1 y 0 s 4 s 3 s 2 s 1 s 0 Overflow? number 11101 00011 11010 no -6 00001 00111 11010 no -6 11100 11001 01000 10101 10110 00011 11000 01011 3
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3) Timing analysis (10 pts) Consider the following sequential logic diagram. Assume the gate delay is 1 ns for 2-AND and 2 ns for 2-XOR. Assume the positive edge-trigged flip-flop delay is
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