2-F-soln

2-F-soln - 1) Two-level logic minimization (10 pts)...

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Consider the logic diagram shown below. A B C OR F 0 1 0 1 0 1 B D B C D a) Please fll out the Following K-map For F as a Function oF A , B , C ,and D . 1 1 1 1 00 01 11 10 CD F 00 01 AB 1 1 1 1 1 1 11 10 b) ±or the K-map derived in part (a) For F , speciFy all the primes and essential primes. Prime Essential 1--1 AD -1-1 BD 1-1- AC X -11- BC X --01 ¯ CD X c) ±ind the minimum two-level logic implementation For F . F = AC + + ¯ 2
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a) For each binary vector below, what does it represent as an Octal number and a Hexadecimal number? Binary Octal Hexadecimal 00111110 076 3E 10100001 241 A1 00111001 071 39 b) Given X and Y below that are 5-bit numbers in 2’s complement form, ±ll in the table of what S should be bit-vector form ( even if the result causes an overflow ). Indicate whether or not there is an overflow and what S is as a number (if S resu ltsinanoverflow ,thenjustputan”x” under the “ S as a number” column). (First two rows provide examples.) X Y S = X Y S as a x 4 x 3 x 2 x 1 x 0 y 4 y 3 y 2 y 1 y 0 s 4 s 3 s 2 s 1 s 0 Overflow? number 11101 00011 11010 no -6 00001 00111 11010 no -6 11100 11001 00011 no 3 01000 10101 10011 yes x 10110 00011 10011 no -13 11000 01011 01101 yes x Guideline : -1 point for each incorrect answer (-10 at most). 3
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Consider the following sequential logic diagram. Assume the gate delay is 1ns for 2-AND and 2 ns for 2-XOR. Assume the positive edge-trigged flip-flop delay is T delay FF = , and Assume the
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This note was uploaded on 01/09/2012 for the course CSE 140 taught by Professor Rosing during the Spring '06 term at UCSD.

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2-F-soln - 1) Two-level logic minimization (10 pts)...

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