# 2-M2 - Midterm 2 ECE 25, Fall 2009 Tuesday, November 24,...

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Midterm 2 ECE 25, Fall 2009 Tuesday, November 24, 2009 Name: PID: Problem Points Score 1 10 2 10 3 10 4 10 Total 40 Consider the following incompletely-speciﬁed Mealy machine (“*” indicates don’t cares). 0/1 A B C 1/* 0/1 0/0 1/1 1/0 Supposeweusethefo l low ingstateencod ing .(Assumethenametheinputvar iab leis I .) State S 1 S 0 A 00 B 10 C 01 Derive the minimum two-level logic for each of the following (you should minimize each logic function separately, no need to worry about sharing logic between logic functions). F = S 1 + = S 0 + = 1

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Consider the following sequential logic diagram. Assume the gate delays are 2ns for 2-AND and 2-OR gates and 1ns for inverters. Assume the positive edge-trigged ﬂip-ﬂop delay is T delay FF = , and setup time is also T setupF F = . Fill out the rest of the timing diagram for A , B , C , D , E , F ,and G . A AND B F G C OR AND D-FF D E CLK 13579 1 1 1 3 1 5 A B C D E 2468 1 0 1 2 1 4 1 6 1 8 17 20 19 22 21 F G 2
3)C lockper iodana lys Consider the following sequential logic diagram where

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## This note was uploaded on 01/09/2012 for the course CSE 140 taught by Professor Rosing during the Spring '06 term at UCSD.

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2-M2 - Midterm 2 ECE 25, Fall 2009 Tuesday, November 24,...

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