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# 2-M2 - Midterm 2 ECE 25 Fall 2009 Tuesday Name PID Problem...

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1) Sequential logic implementation (10 pts) Consider the following incompletely-specified Mealy machine (“*” indicates don’t cares). 0/1 A B C 1/* 0/1 0/0 1/1 1/0 Suppose we use the following state encoding. (Assume the name the input variable is I .) State S 1 S 0 A 00 B 10 C 01 Derive the minimum two-level logic for each of the following (you should minimize each logic function separately, no need to worry about sharing logic between logic functions). F = S 1 + = S 0 + = 1

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2) Timing analysis (10 pts) Consider the following sequential logic diagram. Assume the gate delays are 2 ns for 2-AND and 2-OR gates and 1 ns for inverters. Assume the positive edge-trigged ﬂip-ﬂop delay is T delay F F = 1 ns , and setup time is also T setupFF = 1 ns . Fill out the rest of the timing diagram for A , B , C , D , E , F , and G . A AND B F G C OR AND D-FF D E CLK 1 3 5 7 9 11 13 15 A B C D E 2 4 6 8 10 12 14 16 18 17 20 19 22 21 F G 2
3) Clock period analysis (10 pts) Consider the following sequential logic diagram where A and B

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2-M2 - Midterm 2 ECE 25 Fall 2009 Tuesday Name PID Problem...

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