# 5-F - 1) Delay Analysis (10 pts) Assume 2 ns gate delay for...

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Assume 2ns gate delay for 2-AND. Assume the positive edge-trigged ﬂip-ﬂop delay is T delay FF = 1ns and setup time is also T setupF F = . S 3 + S 2 + A S 1 + S 0 + D-FF S 3 D-FF S 2 D-FF S 1 D-FF S 1 C D E F B What are fnal delays for the following: S + 0 = S 0 = S + 1 = S 1 = S + 2 = S 2 = S + 3 = S 3 = 2

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(a) For each binary vector below, what does it represent if it is interpreted as a Decimal number in conventional binary form (positive only), a Decimal number in 2’s complement form (positive and negative), an Octal number, and a Hexadecimal number? Decimal conventional 2’s complement Binary form form Octal Hexadecimal 000111 001111 011111 111110 111100 111000 (b) What is the minimum number of bits required to represent the following 2’s complement numbers? -27 num bits = 64 num bits = 3
Consider the following incompletely-speciFed Moore machine (“*” indicates don’t cares), and the following state encoding. State table S 1 + S 0 + S 1 S 0 XY =00 01 10 11 F A * B B * 1 B A C C A 1 C * A A * 0 State encoding State S 1 S 0 A 00 B 01 C 10

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## This note was uploaded on 01/09/2012 for the course CSE 140 taught by Professor Rosing during the Spring '06 term at UCSD.

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5-F - 1) Delay Analysis (10 pts) Assume 2 ns gate delay for...

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