5-F-soln

# 5-F-soln - 1) Delay Analysis (10 pts) Assume 2 ns gate...

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Assume 2ns gate delay for 2-AND. Assume the positive edge-trigged ﬂip-ﬂop delay is T delay FF = 1ns and setup time is also T setupF F = . S 3 + S 2 + A S 1 + S 0 + D-FF S 3 D-FF S 2 D-FF S 1 D-FF S 0 C D E F B What are fnal delays for the following: S + 0 =2 n s S 0 =1 n s S + 1 =3 n s S 1 n s S + 2 =5 n s S 2 n s S + 3 =7 n s S 3 n s Clock period = 8 ns 2

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(a) For each binary vector below, what does it represent if it is interpreted as a Decimal number in conventional binary form (positive only), a Decimal number in 2’s complement form (positive and negative), an Octal number, and a Hexadecimal number? Decimal conventional 2’s complement Binary form form Octal Hexadecimal 000111 7 7 07 (just 7 OK) 07 (just 7 OK) 001111 15 15 17 0F (just F OK) 011111 31 31 37 1F 111110 62 -2 76 3E 111100 60 -4 74 3C 111000 56 -8 70 38 (b) What is the minimum number of bits required to represent the following 2’s complement numbers? -27 num bits = 6 64 num bits = 8 3
Consider the following incompletely-speciFed Moore machine (“*” indicates don’t cares), and the following state encoding.

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## This note was uploaded on 01/09/2012 for the course CSE 140 taught by Professor Rosing during the Spring '06 term at UCSD.

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5-F-soln - 1) Delay Analysis (10 pts) Assume 2 ns gate...

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