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Unformatted text preview: EEL4713 Assignment #2 Spring 2009 Assigned: 1/12/2010 Due: 1/22/2010 in class Section 1: Setup There is no setup in this assignment. Section 2: Textbook questions Questions from chapter 2: 2.11.4-6, 2.14.1-3, 2.21.1-2 Section 3: Laboratory In Assignment 4 you will be asked to design a basic single cycle microprocessor that supports the MIPS core instruction set (29 instructions) listed on the front of the green reference sheet that came with your book. In this and the next assignment you will be asked to design several components that you will need to accomplish this daunting task. There will be situations in the design process where you will need to select between two 1-bit signals. In order to solve this problem you will design a 1-bit multiplexer (name your VHDL entity mux1) that will select between two 1-bit input signals, in0 and in1, depending on the value of a third 1-bit select input signal. This third signal, Sel, should cause an output signal, O, to take the value of in0 when Sel=0 or the value of in1 when Sel=1. Compile, simulate and test your design; turn in the VHDL entity and architecture, and a printout of a simulation trace showing the multiplexers output for all possible input combinations. What is the worst-case propagation time from input to output of your 1-bit multiplexer? If you look at the BASIC INSTRUCTION FORMATS section of your green reference sheet you will see that the values rs, rt and rd, each corresponding to 1 of 32 distinct registers, are represented by 5-bit numbers. During the instruction decode process it is sometimes required to select between these 5-bit values. For this reason you will alter your 1-bit multiplexer design to create a new component mux5 that will select between two 5-bit input signals, in0 and in1, depending on the value of a third 1-bit select input signal. depending on the value of a third 1-bit select input signal....
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