eel4713asgt5 - EEL4713 Assignment #5 Spring 2010 Assigned:...

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EEL4713 Assignment #5 Spring 2010 Assigned: 3/02/2010 Due: 4/02/2010 in class Section 1: Setup There is no setup for this assignment. Section 2: Textbook Questions Questions from chapter 4: 4.12.1-3, 4.20.1-2, 4.24.1-3 Section 3: Laboratory In this laboratory you will be modifying your single cycle processor from Assignment 4 in order to implement a pipelined processor. Your processor must support the same 29 instructions required for the single cycle processor, detect potential hazards, and resolve them by forwarding when possible or stalling when not. Please read chapter 4 of your textbook for insight on how this can be done. Begin your design by partitioning your single cycle processor into 5 stages: instruction fetch (IF), instruction decode (ID), execution (EX), memory access (MEM), and write back (WB). Your goal should be to equally divide the propagation delay of your single cycle implementation into the 5 stages. Consult Figure 4.33 in your textbook for inspiration on how you should partition your design. Create four registers to place in between your pipeline stages that will transfer needed data from stage to stage. It is possible to eliminate the “mclk” signal by using the registered input of the altsyncram component as a register between the pipeline stages. Eliminating the “mclk” signal should greatly increase your maximum clock rate and is highly recommended. At this point your processor should be able to execute dependency free code without any problems. Test your processor before moving on. Next, create a table that describes dependencies that may occur when a certain instruction is followed by another instruction and what action you should take in order resolve the dependency (i.e. forwarding or stalling). Below are a few entries from such a table that will help you understand what your table should contain: 1
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R I L S JR LUI B JAL R 1a: exmem.rd=idex.rs(1)
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eel4713asgt5 - EEL4713 Assignment #5 Spring 2010 Assigned:...

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