eel4713asgt6 - EEL4713 Assignment #6 Spring 2010 Assigned:...

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EEL4713 Assignment #6 Spring 2010 Assigned: 3/30/2010 DEMO: 4/20/2010 Due: 4/21/2010 in class Section 1: Setup Download the latest version of the Grid appliance from http://www.grid- appliance.org. Also, install the Cacti and SESC simulators by following the instructions in the “Archer” project Wiki: go to http://archer- project.org , follow the “Educational modules” link, then the link “An assignment on cache modeling with Cacti and SESC”. Section 2: Textbook Questions Questions from chapter 6: 6.3.1-2, 6.15.1-4, 6.18.1-2 Section 3: Laboratory 3.1. Introduction Today’s computers (including memory hierarchies) are designed with the aid of extensive simulations that provide quantitative data to justify design choices. In this problem, you will use a cache hierarchy simulator to investigate tradeoffs in the design of a level-1 cache. In this problem, you will use the “SESC” and “cacti” tools available for execution from the Grid appliance. SESC is a microprocessor simulator (that also simulates the behavior of two-level caches), while Cacti is a program that calculates the speed of caches based on parameters such as size and associativity. In this assignment you will consider a base configuration with two levels of caches: the L1 cache is split into instruction+data caches; the base configuration has both I-cache and D-cache configured with the same parameters: 8Kbytes, 32-byte blocks, direct-mapped. Use default parameters for the L2 cache. Note: each SESC simulation may take 10 or more minutes, so start working on this assignment early! The Grid appliance allows you to run multiple simulations concurrently on remote computers, so you can have more than one simulation running at the same time. Warming up Cacti 3.2 simulator: Cacti is a tool that helps designers determine cache access times, power/energy consumption, among other parameters based on relevant design points entered as inputs to the simulator. It is a fast simulator that uses analytical models to estimate its outputs. Let’s use the Cacti tool to determine the access time of the 1
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L1 cache configured as above as an example. Use a 0.09μm (90nm) technology. The command for a Cacti simulation is: cd cacti ./cacti C B A TECH Nsubbanks Where C is the cache size, B is the clock size, A is the associativity (1=direct-mapped), TECH is the transistor technology, and Nsubbanks is the number of sub-banks (a .pdf document with the full description of the CACTI simulator version 3.2 is included). For example, typing the command “./cacti 8192 32 1 0.09 1 > cacti.out” writes the output of cacti to cacti.out, and the command “grep Access cacti.out” filters the output cacti.out for lines containing the string “Access”. Before moving to the next step, double-check that the access time you obtain is approximately 479ps. Assume a processor clock rate of 3.252GHz
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eel4713asgt6 - EEL4713 Assignment #6 Spring 2010 Assigned:...

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