final-2006-sol - EEL 4713 Computer Architecture Final Exam...

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1 EEL 4713 – Computer Architecture Final Exam Friday, May 5 th , 2006 NAME: Please read each question carefully, to avoid any confusion. This exam should have a total of 14 pages printed double-sided (pages 13 and 14 are scratch space). Before you begin, make sure your copy contains all pages. The exam is closed book, closed notes. Each question has its number of points identified in brackets. GOOD LUCK! QUESTION POINTS SCORED 1 [30] 2 [30] 3 [20] 4 [20] TOTAL
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2 1) [30] Consider two pipelined implementations of MIPS: P1 and P2. - In P1, there are five stages (IF, ID, EX, MEM, WB) as discussed in class and in your lab. Assume there is a split level-1 cache, with perfect (100%) hit rates and 1 cycle hit latency for both the instruction and the data cache. The clock rate is 2GHz. - In P2, the designers realized that if the clock rate could be increased to 2.5GHz, the IF, ID, EX and WB stages would still work correctly. However, at this rate the data cache can no longer be accessed with 1-cycle hit latency – two cycles are needed. So the designers consider adding logic to the pipeline to a) detect that a memory access (load or store) reaches the MEM stage, and b) automatically stall the MEM stage for one cycle when such a memory access instruction reaches the MEM stage. a) [5] What is the maximum throughput (in instructions per second) that each pipeline can achieve? P1: 1 instruction per 0.5E-9 seconds; 2*10^9 instructions per second P2: 2.5*10^9 instructions per second
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3 b) [15] Describe how you would extend the control logic of the original P1 pipeline to deal with the two-cycle MEM stage for memory access instructions in P2. A decoded load or store can generate a signal Cachestall at ID; this propagates through pipeline registers Pull MEM.Cachestall signal to force stall of IF, ID, EX if 1 Reset MEM.Cachestall=0 in the next cycle (e.g. MUX selects 0 or EX.cachestall)
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4 c) [10] Suppose a program X is executed on both P1 and P2; k% of the instruction count of program X is due to loads and stores. What is the maximum value of k such that P2 is faster than P1 when executing program X? (Assume that there are no stalls due to data dependence or branch hazards). Worst case (back-to-back memory):
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This note was uploaded on 01/09/2012 for the course EEL 4713 taught by Professor Staff during the Spring '11 term at University of Florida.

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final-2006-sol - EEL 4713 Computer Architecture Final Exam...

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