Lec4-singlecycle - Outline Introduction The steps of...

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EEL-4713 – Renato Figueiredo EEL-4713 Computer Architecture Designing a Single Cycle Datapath EEL-4713 – Renato Figueiredo Outline ° Introduction ° The steps of designing a processor ° Datapath and timing for register-register operations ° Datapath for logical operations with immediates ° Datapath for load and store operations ° Datapath for branch and jump operations EEL-4713 – Renato Figueiredo Big Picture ° The five classic components of a computer ° Today’s topic: design of a single cycle processor Control Datapath Memory Processor Input Output EEL-4713 – Renato Figueiredo The Big Picture: The Performance Perspective ° Performance of a machine is determined by: Instruction count Clock cycle time Clock cycles per instruction - CPI – will discuss later ° Processor design determines: Clock cycle time Clock cycles per instruction ° Single cycle processor: - Advantage: One clock cycle per instruction - Disadvantage: long cycle time CPI Inst. Count Cycle Time
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EEL-4713 – Renato Figueiredo How to Design a Processor: step-by-step ° 1. Analyze instruction set => datapath requirements The meaning of each instruction is given by the register transfers The datapath must include storage element for ISA registers - And possibly more The datapath must support each register transfer ° 2. Select set of datapath components and establish clocking methodology ° 3. Assemble datapath meeting the requirements ° 4. Analyze implementation of each instruction to determine setting of control points that effects the register transfer. ° 5. Assemble the control logic EEL-4713 – Renato Figueiredo MIPS ISA: instruction formats ° All MIPS instructions are 32 bits long. There are 3 instruction formats: R-type I-type J-type ° The different fields are: op : operation of the instruction rs, rt, rd : the source(s) and destination register specifiers shamt : shift amount funct : selects the variant of the operation in the “op” field address / immediate : address offset or immediate value target address : target address of the jump instruction op target address 0 26 31 6 bits 26 bits op rs rt rd shamt funct 0 6 11 16 21 26 31 6 bits 6 bits 5 bits 5 bits 5 bits 5 bits op rs rt immediate 0 16 21 26 31 6 bits 16 bits 5 bits 5 bits EEL-4713 – Renato Figueiredo *Step 1a: The MIPS “lite” subset for today ° ADD and SUB addU rd, rs, rt subU rd, rs, rt ° OR Immediate: ori rt, rs, imm16 ° LOAD and STORE Word lw rt, rs, imm16 sw rt, rs, imm16 ° BRANCH: beq rs, rt, imm16 op rs rt rd shamt funct 0 6 11 16 21 26 31 6 bits 6 bits 5 bits 5 bits 5 bits 5 bits op rs rt immediate 0 16 21 26 31 6 bits 16 bits 5 bits 5 bits op rs rt immediate 0 16 21 26 31 6 bits 16 bits 5 bits 5 bits op rs rt immediate 0 16 21 26 31 6 bits 16 bits 5 bits 5 bits EEL-4713 – Renato Figueiredo Logical Register Transfers ° RTL gives the meaning of the instructions ° All start by fetching the instruction
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This note was uploaded on 01/09/2012 for the course EEL 4713 taught by Professor Staff during the Spring '11 term at University of Florida.

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Lec4-singlecycle - Outline Introduction The steps of...

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