Lec5-singlecontrol

Lec5-singlecontrol - EEL-4713 Renato Figueiredo EEL-4713 -...

Info iconThis preview shows pages 1–4. Sign up to view the full content.

View Full Document Right Arrow Icon

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
This is the end of the preview. Sign up to access the rest of the document.

Unformatted text preview: EEL-4713 Renato Figueiredo EEL-4713 - Computer Architecture Single-Cycle Control Logic EEL-4713 Renato Figueiredo Recap: The MIPS Subset ° ADD and subtract • add rd, rs, rt • sub rd, rs, rt ° OR Imm: • ori rt, rs, imm16 ° LOAD and STORE • lw rt, rs, imm16 • sw rt, rs, imm16 ° BRANCH: • beq rs, rt, imm16 ° JUMP: • j target op target address 0 26 31 6 bits 26 bits op rs rt rd shamt funct 0 6 11 16 21 26 31 6 bits 6 bits 5 bits 5 bits 5 bits 5 bits op rs rt immediate 0 16 21 26 31 6 bits 16 bits 5 bits 5 bits EEL-4713 Renato Figueiredo Recap: A Single Cycle Datapath 32 ALUctr Clk busW RegWr 32 32 busA 32 busB 5 5 5 Rw Ra Rb 32 32-bit Registers Rs Rt Rt Rd RegDst Extender Mux Mux 32 16 imm16 ALUSrc ExtOp Mux MemtoReg Clk Data In WrEn 32 Adr Data Memory 32 MemWr ALU Instruction Fetch Unit Clk Zero Instruction<31:0> Jump Branch ° We have everything except control signals (underline) • Today’s lecture will show you how to generate the control signals 0 1 0 1 0 1 <21:25> <16:20> <11:15> <0:15> Imm16 Rd Rs Rt EEL-4713 Renato Figueiredo The Big Picture: Where are We Now? ° The Five Classic Components of a Computer ° Today’s Topic: Designing the Control for the Single Cycle Datapath Control Datapath Memory Processor Input Output EEL-4713 Renato Figueiredo Outline of Today’s Lecture ° Recap and Introduction ° Control for Register-Register & Or Immediate instructions ° Control signals for Load, Store, Branch, & Jump ° Building a local controller: ALU Control ° The main controller ° Summary EEL-4713 Renato Figueiredo RTL: The ADD Instruction ° add rd, rs, rt • mem[PC] Fetch the instruction from memory • R[rd] <- R[rs] + R[rt] The actual operation • PC <- PC + 4 Calculate the next instruction’s address op rs rt rd shamt funct 0 6 11 16 21 26 31 6 bits 6 bits 5 bits 5 bits 5 bits 5 bits EEL-4713 Renato Figueiredo Instruction Fetch Unit at the Beginning of Add / Subtract 30 30 SignExt 30 16 imm16 Mux 0 1 Adder “1” PC Clk Adder 30 30 Branch = previous Zero = previous “00” Addr<31:2> Instruction Memory Addr<1:0> 32 Mux 1 0 26 4 PC<31:28> Target 30 ° Fetch the instruction from Instruction memory: Instruction <- mem[PC] • This is the same for all instructions Jump = previous Instruction<15:0> Instruction<31:0> 30 Instruction<25:0> EEL-4713 Renato Figueiredo The Single Cycle Datapath during Add and Subtract 32 ALUctr = Add or Subtract Clk busW RegWr = 1 32 32 busA 32 busB 5 5 5 Rw Ra Rb 32 32-bit Registers Rs Rt Rt Rd RegDst = 1 Extender Mux Mux 32 16 imm16 ALUSrc = 0 ExtOp = x Mux MemtoReg = 0 Clk Data In WrEn 32 Adr Data Memory 32 MemWr = 0 ALU Instruction Fetch Unit Clk Zero Instruction<31:0> Jump = 0 Branch = 0 ° R[rd] <- R[rs] + / - R[rt] 0 1 0 1 0 1 <21:25> <16:20> <11:15> <0:15> Imm16 Rd Rs Rt op rs rt rd shamt funct 0 6 11 16 21 26 31 EEL-4713 Renato Figueiredo The Single Cycle Datapath during Add and Subtract 32 ALUctr = Add or Subtract Clk busW RegWr = 1 32 32 busA 32 busB 5 5 5 Rw Ra Rb 32 32-bit Registers...
View Full Document

This note was uploaded on 01/09/2012 for the course EEL 4713 taught by Professor Staff during the Spring '11 term at University of Florida.

Page1 / 10

Lec5-singlecontrol - EEL-4713 Renato Figueiredo EEL-4713 -...

This preview shows document pages 1 - 4. Sign up to view the full document.

View Full Document Right Arrow Icon
Ask a homework question - tutors are online