Lec6-multicycle - Outline of today s lecture Recap and...

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Unformatted text preview: Outline of today s lecture Recap and Introduction Introduction to the Concept of Multiple Cycle Processor Multiple Cycle Implementation of R-type Instructions What is a Multiple Cycle Delay Path and Why is it Bad? Multiple Cycle Implementation of Or Immediate Multiple Cycle Implementation of Load and Store Putting it all Together EEL-4713 Computer Architecture Designing a Multiple-Cycle Processor 1 EEL-4713 Ann Gordon - Ross 2 EEL-4713 Ann Gordon - Ross Abstract view of our single cycle processor op fun ExtOp ALUSrc ALUctr What s wrong with our CPI=1 processor? Arithmetic & Logical PC Inst Memory Reg File mux Main Control ALU control ALU mux Reg File Load PC MemWr RegDst RegWr Inst Memory Equal nPC_sel MemRd MemWr Store PC Branch PC mux Reg File Critical Path ALU Data Mem mux Reg File Inst Memory Inst Memory Reg File Reg File mux ALU mux Data Mem PC Ext ALU Result Store Instruction Fetch Next PC Register Fetch Mem Access Reg. Wrt cmp Data Mem Long Cycle Time All instructions take as much time as the slowest Real memory is not so nice as our idealized memory looks like an FSM with PC as state 3 EEL-4713 Ann Gordon - Ross cannot always get the job done in one (short) cycle 4 EEL-4713 Ann Gordon - Ross Drawbacks of this single cycle processor Long cycle time: Cycle time is much longer than needed for all other instructions. Examples: R-type instructions do not require data memory access Jump does not require ALU operation nor data memory access Overview of a multiple cycle implementation The root of the single cycle processor s problems: The cycle time has to be long enough for the slowest instruction Solution: Break the instruction into smaller steps Execute each step (instead of the entire instruction) in one cycle - - Cycle time: time it takes to execute the longest step All the steps have similar length Need for multiple functional units E.g. instruction/data memory, adders This is the essence of the multiple cycle processor The advantages of the multiple cycle processor: Cycle time is much shorter Different instructions take different number of cycles to complete (for now) - Load takes five cycles - Jump only takes three cycles Allows a functional unit to be used more than once per instruction 5 EEL-4713 Ann Gordon - Ross 6 EEL-4713 Ann Gordon - Ross What and when: When designing multi-cycle implementations, you must think about: What to do on each cycle When results are ready for next cycle Overview: Control State Diagram Ifetch Fetch and store in IR PC=PC+4 Rfetch/Decode Decode operation Index registers Register operands In busA, busB BrComplete beq Finish branch Calculate the Target address Select mux, Write PC AdrCal ALU Computes rs+imm lw or sw sw What to do on each cycle: Always need to fetch instruction Always need to decode instruction (know what to do next) Next need to perform actual operation (varies from instruction to instruction) E.g.: - - - Load will require address calculation, memory read, reg write Branch will require comparison and PC update R-type will require ALU operation, reg write lw LWmem Read mem. with address calculated above Rtype SWMem Write rt to memory address calc. above Ori OriExec ALU has inputs and control set, can compute RExec ALU has inputs and control set, can compute Rfinish LWwr Latch data read from memory in rt OriFinish Latch ALU computed result in rd Latch ALU computed result in rt 7 EEL-4713 Ann Gordon - Ross 8 EEL-4713 Ann Gordon - Ross Example: the five steps of a Load instruction Instruction Fetch Clk PC Old Value Clk-to-Q New Value Old Value Old Value Old Value Old Value Old Value Old Value Delay through Extender & Mux Old Value Old Value Data Memory Access Time busW Old Value New Instruction Memory Access Time New Value Delay through Control Logic New Value New Value New Value Multicycle datapath Reg Wr Instr Decode / Reg. Fetch Address Data Memory Similar to the single-cycle datapath; use latches for instruction and branch target address Control signals generated for multiple clock cycles per instruction FSM PCWrCond=0 Zero 32 32 32 0 1 32 32 RAdr Rs 32 Rt Rt 0 Rd 1 5 5 0 1 32 Rs, Rt, Rd, Op, Func ALUctr ExtOp ALUSrc RegWr busA busB Address PCWr=0 PCSrc=x RegDst=x RegWr=0 ALUSelA=0 1 0 32 0 1 2 3 32 BrWr=1 32 IorD=x PC Mux MemWr=0 IRWr=0 Target Mux Zero ALU Mux Instruction Reg Ra Rb Rw busW busB 32 busA Register File Write Time New Value Register File Access Time New Value New Value ALU Delay New Value 32 Ideal Memory Reg File 4 Mux WrAdr 32 Din Dout 32 Beq Rtype Ori Memory << 2 Control Op Func 6 6 Imm 16 ALU Control Extend ALUSelB=10 32 : ALUOp=Add 9 EEL-4713 Ann Gordon - Ross 10 EEL-4713 Ann Gordon - Ross ExtOp=1 Overview: Control State Diagram Ifetch Fetch and store in IR PC=PC+4 Cycle 1: Fetch BrComplete beq Finish branch Calculate the Target address Select mux, Write PC Rfetch/Decode Decode operation Index registers Register operands In busA, busB Ifetch AdrCal ALU Computes rs+imm AdrCal lw or sw sw lw LWmem Read mem. with address calculated above Rtype SWMem Write rt to memory address calc. above Ori OriExec ALU has inputs and control set, can compute 1: ExtOp ALUSelA ALUSelB=11 ALUOp=Add x: MemtoReg PCSrc ALUOp=Add 1: PCWr, IRWr x: PCWrCond RegDst, Mem2R Others: 0s Rfetch/Decode ALUOp=Add 1: BrWr, ExtOp ALUSelB=10 x: RegDst, PCSrc IorD, MemtoReg Others: 0s BrComplete beq ALUOp=Sub ALUSelB=01 x: IorD, Mem2Reg RegDst, ExtOp 1: PCWrCond ALUSelA PCSrc lw or sw sw SWMem 1: ExtOp MemWr ALUSelA ALUSelB=11 ALUOp=Add x: PCSrc,RegDst MemtoReg RExec lw ALUSelA, IorD ALUSelB=11 ALUOp=Add x: MemtoReg PCSrc 1: ExtOp LWmem Rtype Ori OriExec ALUOp=Or 1: ALUSelA ALUSelB=11 x: MemtoReg IorD, PCSrc ALU has inputs and control set, can compute RExec 1: RegDst ALUSelA ALUSelB=01 ALUOp=Rtype x: PCSrc, IorD MemtoReg ExtOp Rfinish LWwr Latch data read from memory in rt OriFinish Latch ALU computed result in rd Latch ALU computed result in rt LWwr 1: ALUSelA RegWr, ExtOp MemtoReg ALUSelB=11 ALUOp=Add x: PCSrc IorD Rfinish OriFinish ALUOp=Or x: IorD, PCSrc ALUSelB=11 1: ALUSelA RegWr ALUOp=Rtype 1: RegDst, RegWr ALUselA ALUSelB=01 x: IorD, PCSrc ExtOp 11 EEL-4713 Ann Gordon - Ross 12 EEL-4713 Ann Gordon - Ross 1 Instruction fetch cycle: beginning Every cycle begins right AFTER the clock tick: mem[PC] PC<31:0> + 4 Clk One Logic Clock Cycle You are here! PCWr=? PC Clk 1 Instruction fetch cycle: end Every cycle ends AT the next clock tick (storage element updates): IR <-- mem[PC] PC<31:0> <-- PC<31:0> + 4 Clk One Logic Clock Cycle You are here! PCWr=1 PC 32 32 MemWr=? RAdr IRWr=? Instruction Reg 4 32 32 32 32 32 MemWr=0 RAdr IRWr=1 00 ALU ALU 32 Instruction Reg 32 Clk 32 4 32 32 Ideal Memory 32 32 WrAdr Din Dout 32 ALU Control ALUop=? 32 Ideal Memory WrAdr Din Dout ALU Control ALUOp = Add 32 32 Clk 13 EEL-4713 Ann Gordon - Ross 14 EEL-4713 Ann Gordon - Ross Clk 1 Instruction Fetch Cycle: Overall Picture Ifetch 1. 2. Latch IR=mem[PC] Set PC=PC+4 ALUOp=Add 1: PCWr, IRWr x: PCWrCond RegDst, Mem2R Others: 0s Fetch and store in IR PC=PC+4 Cycle 2: Register fetch, decode Ifetch ALUOp=Add 1: PCWr, IRWr x: PCWrCond RegDst, Mem2R Others: 0s Rfetch/Decode ALUOp=Add 1: BrWr, ExtOp ALUSelB=10 x: RegDst, PCSrc IorD, MemtoReg Others: 0s BrComplete beq ALUOp=Sub ALUSelB=01 x: IorD, Mem2Reg RegDst, ExtOp 1: PCWrCond ALUSelA PCSrc AdrCal PCWr=1 PCWrCond=x Zero IorD=0 MemWr=0 IRWr=1 32 32 PCSrc=0 ALUSelA=0 0 1 32 busB 32 1 0 32 0 1 2 3 32 BrWr=0 32 1: ExtOp ALUSelA ALUSelB=11 ALUOp=Add x: MemtoReg PCSrc lw or sw sw SWMem 1: ExtOp MemWr ALUSelA ALUSelB=11 ALUOp=Add x: PCSrc,RegDst MemtoReg Target lw ALUSelA, IorD ALUSelB=11 ALUOp=Add x: MemtoReg PCSrc 1: ExtOp LWmem Rtype Ori OriExec ALUOp=Or 1: ALUSelA ALUSelB=11 x: MemtoReg IorD, PCSrc RExec 1: RegDst Mux PC 32 32 0 1 32 32 Zero ALU RAdr Ideal Memory busA ALUSelA ALUSelB=01 ALUOp=Rtype x: PCSrc, IorD MemtoReg ExtOp Mux Instruction Reg 15 EEL-4713 Ann Gordon - Ross Mux 4 WrAdr 32 Din Dout 32 LWwr ALU Control ALUOp=Add ALUSelB=00 1: ALUSelA RegWr, ExtOp MemtoReg ALUSelB=11 ALUOp=Add x: PCSrc IorD Rfinish OriFinish ALUOp=Or x: IorD, PCSrc ALUSelB=11 1: ALUSelA RegWr ALUOp=Rtype 1: RegDst, RegWr ALUselA ALUSelB=01 x: IorD, PCSrc ExtOp 16 EEL-4713 Ann Gordon - Ross 2 Register Fetch / Instruction Decode busA <- RegFile[rs] ; busB <- RegFile[rt] ; ALU can be used to compute branch target address (next slide) PCWr=0 PCWrCond=0 Zero IorD=x PC 32 32 32 0 1 32 32 RAdr 2 Register Fetch / Instruction Decode (Continue) busA <- Reg[rs] ; busB <- Reg[rt] ; Target <- PC + SignExt(Imm16)*4 Generate control signals PCSrc=x PCWr=0 1 0 32 0 1 2 3 32 32 Rfetch/Decode ALUOp=Add 1: BrWr, ExtOp ALUSelB=10 x: RegDst, PCSrc IorD, MemtoReg Others: 0s Decode operation Index registers Register operands In busA, busB PCWrCond=0 Zero IorD=x MemWr=0 IRWr=0 32 32 Rs 32 Rt Rt 0 Rd 1 5 5 PCSrc=x 1 0 32 0 1 2 3 32 BrWr=1 32 MemWr=0 IRWr=0 32 RegDst=x RegWr=0 ALUSelA=x 0 1 32 RegDst=x RegWr=0 ALUSelA=0 0 1 32 Target Mux Mux PC Zero 32 32 32 32 32 0 1 Rs 32 Rt Rt 0 Rd 1 5 5 Zero ALU Mux Mux Instruction Reg Instruction Reg Ra Rb Rw busW busB 32 busA RAdr Ra Rb Rw busW busB 32 busA 17 EEL-4713 Ann Gordon - Ross Cycle 3: Branch completion Ifetch ALUOp=Add 1: PCWr, IRWr x: PCWrCond RegDst, Mem2R Others: 0s AdrCal 19 EEL-4713 Ann Gordon - Ross Mux lw LWwr Mux ALU Ideal Memory Reg File 4 WrAdr 32 Din Dout Ideal Memory Reg File 4 Mux Mux WrAdr 32 Din Dout 32 ALU Control Go to the Op Control Func 6 6 Imm 16 ALUSelB=xx ALUOp=xx Beq Rtype Ori Memory << 2 Control Op Func 6 6 Imm 16 ALU Control Extend ALUSelB=10 32 : ALUOp=Add 18 EEL-4713 Ann Gordon - Ross ExtOp=1 3 Branch Completion BrComplete beq ALUOp=Sub ALUSelB=01 x: IorD, Mem2Reg RegDst, ExtOp 1: PCWrCond ALUSelA PCSrc BrComplete ALUOp=Sub ALUSelB=01 x: IorD, Mem2Reg RegDst, ExtOp 1: PCWrCond ALUSelA PCSrc Finish branch Calculate the Target address Select mux, Write PC Rfetch/Decode ALUOp=Add 1: BrWr, ExtOp ALUSelB=10 x: RegDst, PCSrc IorD, MemtoReg Others: 0s if (busA == busB) PC <- Target 1: ExtOp ALUSelA ALUSelB=11 ALUOp=Add x: MemtoReg PCSrc lw or sw sw SWMem 1: ExtOp MemWr ALUSelA ALUSelB=11 ALUOp=Add x: PCSrc,RegDst MemtoReg PCWr=0 Rtype RExec 1: RegDst Ori OriExec ALUOp=Or 1: ALUSelA ALUSelB=11 x: MemtoReg IorD, PCSrc PCWrCond=1 Zero IorD=x MemWr=0 IRWr=0 32 32 Rs 32 Rt Rt 0 Rd 1 PCSrc=1 ALUSelA=1 0 1 32 1 0 32 0 1 2 3 32 BrWr=0 32 RegDst=x RegWr=0 Target Mux 1: ExtOp LWmem ALUSelA, IorD ALUSelB=11 ALUOp=Add x: MemtoReg PCSrc 1: ALUSelA RegWr, ExtOp MemtoReg ALUSelB=11 ALUOp=Add x: PCSrc IorD ALUSelA ALUSelB=01 ALUOp=Rtype x: PCSrc, IorD MemtoReg ExtOp PC 32 32 0 1 32 32 Zero ALU Mux Instruction Reg RAdr 5 5 Ra Rb Rw busW busB 32 busA Mux Ideal Memory Reg File 4 Mux Rfinish OriFinish ALUOp=Or x: IorD, PCSrc ALUSelB=11 1: ALUSelA RegWr ALUOp=Rtype 1: RegDst, RegWr ALUselA ALUSelB=01 x: IorD, PCSrc ExtOp WrAdr 32 Din Dout 32 << 2 Imm 16 ALU Control Extend ALUSelB=01 32 ALUOp=Sub 20 EEL-4713 Ann Gordon - Ross ExtOp=x Cycle 3: Rtype execution Ifetch ALUOp=Add 1: PCWr, IRWr x: PCWrCond RegDst, Mem2R Others: 0s 3 R-type Execution Rfetch/Decode ALUOp=Add 1: BrWr, ExtOp ALUSelB=10 x: RegDst, PCSrc IorD, MemtoReg Others: 0s BrComplete beq ALUOp=Sub ALUSelB=01 x: IorD, Mem2Reg RegDst, ExtOp 1: PCWrCond ALUSelA PCSrc ALU Output <- busA op busB Jump PCWr=0 PCWrCond=0 Zero IorD=x PC MemWr=0 IRWr=0 32 32 32 32 0 1 32 32 RAdr Rs 32 Rt RExec AdrCal 1: ExtOp ALUSelA ALUSelB=11 ALUOp=Add x: MemtoReg PCSrc 1: RegDst ALUSelA ALUSelB=01 ALUOp=Rtype x: PCSrc, IorD MemtoReg ExtOp ALU has inputs and control set, can compute PCSrc=x ALUSelA=1 0 1 32 1 0 32 0 1 2 3 32 BrWr=0 Target 32 JumpAddr Zero ALU lw or sw sw SWMem 1: ExtOp MemWr ALUSelA ALUSelB=11 ALUOp=Add x: PCSrc,RegDst MemtoReg RegDst=1 RegWr=0 Mux lw ALUSelA, IorD ALUSelB=11 ALUOp=Add x: MemtoReg PCSrc 1: ExtOp LWmem Rtype Ori OriExec ALUOp=Or 1: ALUSelA ALUSelB=11 x: MemtoReg IorD, PCSrc Mux RExec 1: RegDst Instruction Reg ALUSelA ALUSelB=01 ALUOp=Rtype x: PCSrc, IorD MemtoReg ExtOp 5 5 Ra Rb Rw busW busB 32 busA Mux Ideal Memory Rt 0 Rd 1 Reg File 4 Mux WrAdr 32 Din Dout 32 LWwr 1: ALUSelA RegWr, ExtOp MemtoReg ALUSelB=11 ALUOp=Add x: PCSrc IorD Rfinish OriFinish ALUOp=Or x: IorD, PCSrc ALUSelB=11 1: ALUSelA RegWr 1 Mux 0 ALUOp=Rtype 1: RegDst, RegWr ALUselA ALUSelB=01 x: IorD, PCSrc ExtOp << 2 ALU Control Funct Imm 16 Extend 32 ExtOp=x 22 EEL-4713 Ann Gordon - Ross MemtoReg=x ALUOp=Rtype ALUSelB=01 21 EEL-4713 Ann Gordon - Ross Cycle 4: Rtype completion Ifetch ALUOp=Add 1: PCWr, IRWr x: PCWrCond RegDst, Mem2R Others: 0s 4 R-type Completion Rfetch/Decode BrComplete beq ALUOp=Sub ALUSelB=01 x: IorD, Mem2Reg RegDst, ExtOp 1: PCWrCond ALUSelA PCSrc Rfinish R[rd] <- ALU Output PCWr=0 PCWrCond=0 Zero IorD=x PC MemWr=0 IRWr=0 32 32 32 32 0 1 32 32 RAdr Rs 32 Rt Rt 0 Rd 1 5 5 AdrCal 1: ExtOp ALUSelA ALUSelB=11 ALUOp=Add x: MemtoReg PCSrc lw or sw sw SWMem 1: ExtOp MemWr ALUSelA ALUSelB=11 ALUOp=Add x: PCSrc,RegDst MemtoReg ALUOp=Add 1: BrWr, ExtOp ALUSelB=10 x: RegDst, PCSrc IorD, MemtoReg Others: 0s ALUOp=Rtype 1: RegDst, RegWr ALUselA ALUSelB=01 x: IorD, PCSrc ExtOp Latch ALU computed result in rd PCSrc=x ALUSelA=1 0 1 32 1 0 32 0 1 2 3 32 BrWr=0 32 RegDst=1 RegWr=1 Target Mux lw ALUSelA, IorD ALUSelB=11 ALUOp=Add x: MemtoReg PCSrc 1: ExtOp LWmem Rtype Ori OriExec ALUOp=Or 1: ALUSelA ALUSelB=11 x: MemtoReg IorD, PCSrc RExec 1: RegDst Zero ALU Mux Instruction Reg ALUSelA ALUSelB=01 ALUOp=Rtype x: PCSrc, IorD MemtoReg ExtOp Ra Rb Rw busW busB 32 busA Mux Ideal Memory Reg File 4 Mux WrAdr 32 Din Dout 32 LWwr 1: ALUSelA RegWr, ExtOp MemtoReg ALUSelB=11 ALUOp=Add x: PCSrc IorD Rfinish OriFinish ALUOp=Or x: IorD, PCSrc ALUSelB=11 1: ALUSelA RegWr 1 Mux 0 ALUOp=Rtype 1: RegDst, RegWr ALUselA ALUSelB=01 x: IorD, PCSrc ExtOp << 2 ALU Control Imm 16 Extend 32 ExtOp=x 24 EEL-4713 Ann Gordon - Ross MemtoReg=0 ALUOp=Rtype ALUSelB=01 23 EEL-4713 Ann Gordon - Ross Cycle 3: Ori execution Ifetch ALUOp=Add 1: PCWr, IRWr x: PCWrCond RegDst, Mem2R Others: 0s 3 Ori Execution Rfetch/Decode ALUOp=Add 1: BrWr, ExtOp ALUSelB=10 x: RegDst, PCSrc IorD, MemtoReg Others: 0s BrComplete beq ALUOp=Sub ALUSelB=01 x: IorD, Mem2Reg RegDst, ExtOp 1: PCWrCond ALUSelA PCSrc ALU output <- busA or ZeroExt[Imm16] ALUOp=Or OriExec 1: ALUSelA ALUSelB=11 x: MemtoReg IorD, PCSrc ALUOp=Or 1: ALUSelA ALUSelB=11 x: MemtoReg IorD, PCSrc AdrCal 1: ExtOp ALUSelA ALUSelB=11 ALUOp=Add x: MemtoReg PCSrc PCWr=0 PCWrCond=0 Zero IorD=x MemWr=0 IRWr=0 32 32 Rs 32 Rt Rt 0 Rd 1 5 5 PCSrc=x RegDst=0 RegWr=0 ALUSelA=1 0 1 32 1 0 32 0 1 2 3 32 BrWr=0 32 lw or sw sw SWMem 1: ExtOp MemWr ALUSelA ALUSelB=11 ALUOp=Add x: PCSrc,RegDst MemtoReg Target Mux lw ALUSelA, IorD ALUSelB=11 ALUOp=Add x: MemtoReg PCSrc 1: ExtOp LWmem Rtype RExec 1: RegDst Ori OriExec ALUOp=Or 1: ALUSelA ALUSelB=11 x: MemtoReg IorD, PCSrc PC 32 32 0 1 32 ALUSelA ALUSelB=01 ALUOp=Rtype x: PCSrc, IorD MemtoReg ExtOp Zero ALU Mux Instruction Reg RAdr Ra Rb Rw busW busB 32 busA Mux Ideal Memory 32 Reg File 4 Mux WrAdr 32 Din Dout 32 LWwr 1: ALUSelA RegWr, ExtOp MemtoReg ALUSelB=11 ALUOp=Add x: PCSrc IorD Rfinish OriFinish ALUOp=Or x: IorD, PCSrc ALUSelB=11 1: ALUSelA RegWr ALUOp=Rtype 1: RegDst, RegWr ALUselA ALUSelB=01 x: IorD, PCSrc ExtOp 1 Mux 0 << 2 ALU Control Imm 16 Extend 32 ExtOp=0 25 EEL-4713 Ann Gordon - Ross 26 EEL-4713 Ann Gordon - Ross MemtoReg=x ALUOp=Or ALUSelB=11 Cycle 4: Ori completion Ifetch ALUOp=Add 1: PCWr, IRWr x: PCWrCond RegDst, Mem2R Others: 0s 4 Ori Completion Rfetch/Decode ALUOp=Add 1: BrWr, ExtOp ALUSelB=10 x: RegDst, PCSrc IorD, MemtoReg Others: 0s BrComplete beq ALUOp=Sub ALUSelB=01 x: IorD, Mem2Reg RegDst, ExtOp 1: PCWrCond ALUSelA PCSrc ALUOp=Or OriFinish Reg[rt] <- ALU output PCWr=0 PCWrCond=0 Zero IorD=x PC 32 32 32 0 1 32 RAdr AdrCal 1: ExtOp ALUSelA ALUSelB=11 ALUOp=Add x: MemtoReg PCSrc x: IorD, PCSrc ALUSelB=11 1: ALUSelA RegWr Latch ALU computed result in rt PCSrc=x ALUSelA=1 0 1 32 1 0 32 0 1 2 3 32 BrWr=0 32 lw or sw sw SWMem 1: ExtOp MemWr ALUSelA ALUSelB=11 ALUOp=Add x: PCSrc,RegDst MemtoReg MemWr=0 IRWr=0 32 RegDst=0 RegWr=1 Target Mux lw ALUSelA, IorD ALUSelB=11 ALUOp=Add x: MemtoReg PCSrc 1: ExtOp LWmem Rtype RExec 1: RegDst Ori OriExec ALUOp=Or 1: ALUSelA ALUSelB=11 x: MemtoReg IorD, PCSrc ALUSelA ALUSelB=01 ALUOp=Rtype x: PCSrc, IorD MemtoReg ExtOp Rs 32 Rt Rt 0 Rd 1 5 5 Zero ALU Mux Instruction Reg Ra Rb Rw busW busB 32 busA Mux Ideal Memory 32 Reg File 4 Mux WrAdr 32 Din Dout 32 LWwr 1: ALUSelA RegWr, ExtOp MemtoReg ALUSelB=11 ALUOp=Add x: PCSrc IorD Rfinish OriFinish ALUOp=Or x: IorD, PCSrc ALUSelB=11 1: ALUSelA RegWr ALUOp=Rtype 1: RegDst, RegWr ALUselA ALUSelB=01 x: IorD, PCSrc ExtOp 1 Mux 0 << 2 ALU Control Imm 16 Extend 32 ExtOp=0 27 EEL-4713 Ann Gordon - Ross 28 EEL-4713 Ann Gordon - Ross MemtoReg=0 ALUOp=Or ALUSelB=11 Cycle 3: Address calculation Ifetch ALUOp=Add 1: PCWr, IRWr x: PCWrCond RegDst, Mem2R Others: 0s 3 Memory Address Calculation BrComplete beq ALUOp=Sub ALUSelB=01 x: IorD, Mem2Reg RegDst, ExtOp 1: PCWrCond ALUSelA PCSrc Rfetch/Decode ALUOp=Add 1: BrWr, ExtOp ALUSelB=10 x: RegDst, PCSrc IorD, MemtoReg Others: 0s ALU output <- busA + SignExt[Imm16] PCWr=0 PCWrCond=0 Zero IorD=x PC 32 32 32 0 1 32 RAdr AdrCal 1: ExtOp ALUSelA ALUSelB=11 ALUOp=Add x: MemtoReg PCSrc 1: ExtOp ALUSelA ALUSelB=11 ALUOp=Add x: MemtoReg PCSrc AdrCal ALU Computes rs+imm PCSrc=x RegDst=x RegWr=0 ALUSelA=1 0 1 32 1 0 32 0 1 2 3 32 BrWr=0 32 lw or sw sw SWMem 1: ExtOp MemWr ALUSelA ALUSelB=11 ALUOp=Add x: PCSrc,RegDst MemtoReg MemWr=0 IRWr=0 32 Target Mux lw ALUSelA, IorD ALUSelB=11 ALUOp=Add x: MemtoReg PCSrc 1: ExtOp LWmem Rtype RExec 1: RegDst Ori OriExec ALUOp=Or 1: ALUSelA ALUSelB=11 x: MemtoReg IorD, PCSrc ALUSelA ALUSelB=01 ALUOp=Rtype x: PCSrc, IorD MemtoReg ExtOp Rs 32 Rt Rt 0 Rd 1 5 5 Zero ALU Mux Instruction Reg Ra Rb Rw busW busB 32 busA Mux Ideal Memory 32 Reg File 4 Mux WrAdr 32 Din Dout 32 LWwr 1: ALUSelA RegWr, ExtOp MemtoReg ALUSelB=11 ALUOp=Add x: PCSrc IorD Rfinish OriFinish ALUOp=Or x: IorD, PCSrc ALUSelB=11 1: ALUSelA RegWr ALUOp=Rtype 1: RegDst, RegWr ALUselA ALUSelB=01 x: IorD, PCSrc ExtOp 1 Mux 0 << 2 ALU Control Imm 16 Extend 32 ExtOp=1 29 EEL-4713 Ann Gordon - Ross 30 EEL-4713 Ann Gordon - Ross MemtoReg=x ALUOp=Add ALUSelB=11 Cycle 4: Memory access, store Ifetch ALUOp=Add 1: PCWr, IRWr x: PCWrCond RegDst, Mem2R Others: 0s 4 Memory Access for Store BrComplete beq ALUOp=Sub ALUSelB=01 x: IorD, Mem2Reg RegDst, ExtOp 1: PCWrCond ALUSelA PCSrc Rfetch/Decode ALUOp=Add 1: BrWr, ExtOp ALUSelB=10 x: RegDst, PCSrc IorD, MemtoReg Others: 0s mem[ALU output] <- busB PCWr=0 PCWrCond=0 Zero IorD=x PC 32 32 32 0 1 32 32 RAdr AdrCal 1: ExtOp SWmem MemWr ALUSelA ALUSelB=11 ALUOp=Add x: PCSrc,RegDst MemtoReg PCSrc=x Write rt to memory address calc. above BrWr=0 1 0 32 1: ExtOp ALUSelA ALUSelB=11 ALUOp=Add x: MemtoReg PCSrc MemWr=1 IRWr=0 32 RegDst=x RegWr=0 ALUSelA=1 0 1 32 Target Mux lw or sw sw SWMem 1: ExtOp MemWr ALUSelA ALUSelB=11 ALUOp=Add x: PCSrc,RegDst MemtoReg lw 1: ExtOp LWmem ALUSelA, IorD ALUSelB=11 ALUOp=Add x: MemtoReg PCSrc Rtype Ori OriExec ALUOp=Or 1: ALUSelA ALUSelB=11 x: MemtoReg IorD, PCSrc Rs 32 Rt Rt 0 Rd 1 5 5 Zero ALU Mux Instruction Reg RExec 1: RegDst Ra Rb Rw busW busB 32 busA ALUSelA ALUSelB=01 ALUOp=Rtype x: PCSrc, IorD MemtoReg ExtOp 32 0 1 2 3 32 Mux Ideal Memory Reg File 4 Mux WrAdr 32 Din Dout 32 LWwr 1: ALUSelA RegWr, ExtOp MemtoReg ALUSelB=11 ALUOp=Add x: PCSrc IorD Rfinish OriFinish ALUOp=Or x: IorD, PCSrc ALUSelB=11 1: ALUSelA RegWr 1 Mux 0 << 2 ALU Control ALUOp=Rtype 1: RegDst, RegWr ALUselA ALUSelB=01 x: IorD, PCSrc ExtOp Imm 16 Extend 32 ExtOp=1 32 EEL-4713 Ann Gordon - Ross MemtoReg=x ALUOp=Add ALUSelB=11 31 EEL-4713 Ann Gordon - Ross Cycle 4: Memory access, load Ifetch ALUOp=Add 1: PCWr, IRWr x: PCWrCond RegDst, Mem2R Others: 0s 4 Memory Access for Load BrComplete beq ALUOp=Sub ALUSelB=01 x: IorD, Mem2Reg RegDst, ExtOp 1: PCWrCond ALUSelA PCSrc Rfetch/Decode ALUOp=Add 1: BrWr, ExtOp ALUSelB=10 x: RegDst, PCSrc IorD, MemtoReg Others: 0s Mem Dout <- mem[ALU output] PCWr=0 PCWrCond=0 Zero IorD=1 PC 32 32 32 0 1 32 RAdr AdrCal 1: ExtOp ALUSelA ALUSelB=11 ALUOp=Add x: MemtoReg PCSrc 1: ExtOp LWmem ALUSelA, IorD ALUSelB=11 ALUOp=Add x: MemtoReg PCSrc Read mem. with address calculated above PCSrc=x RegDst=0 RegWr=0 ALUSelA=1 0 1 32 1 0 32 0 1 2 3 32 BrWr=0 32 lw or sw sw SWMem 1: ExtOp MemWr ALUSelA ALUSelB=11 ALUOp=Add x: PCSrc,RegDst MemtoReg MemWr=0 IRWr=0 32 Target Mux lw ALUSelA, IorD ALUSelB=11 ALUOp=Add x: MemtoReg PCSrc 1: ExtOp LWmem Rtype RExec 1: RegDst Ori OriExec ALUOp=Or 1: ALUSelA ALUSelB=11 x: MemtoReg IorD, PCSrc ALUSelA ALUSelB=01 ALUOp=Rtype x: PCSrc, IorD MemtoReg ExtOp Rs 32 Rt Rt 0 Rd 1 5 5 Zero ALU Mux Instruction Reg Ra Rb Rw busW busB 32 busA Mux Ideal Memory 32 Reg File 4 Mux WrAdr 32 Din Dout 32 LWwr 1: ALUSelA RegWr, ExtOp MemtoReg ALUSelB=11 ALUOp=Add x: PCSrc IorD Rfinish OriFinish ALUOp=Or x: IorD, PCSrc ALUSelB=11 1: ALUSelA RegWr ALUOp=Rtype 1: RegDst, RegWr ALUselA ALUSelB=01 x: IorD, PCSrc ExtOp 1 Mux 0 << 2 ALU Control Imm 16 Extend 32 ExtOp=1 33 EEL-4713 Ann Gordon - Ross 34 EEL-4713 Ann Gordon - Ross MemtoReg=x ALUOp=Add ALUSelB=11 Cycle 4: Memory access, load Ifetch ALUOp=Add 1: PCWr, IRWr x: PCWrCond RegDst, Mem2R Others: 0s 5 Write Back for Load BrComplete beq ALUOp=Sub ALUSelB=01 x: IorD, Mem2Reg RegDst, ExtOp 1: PCWrCond ALUSelA PCSrc Rfetch/Decode ALUOp=Add 1: BrWr, ExtOp ALUSelB=10 x: RegDst, PCSrc IorD, MemtoReg Others: 0s Reg[rt] <- Mem Dout PCWr=0 PCWrCond=0 Zero IorD=x PC 32 32 32 0 1 32 RAdr AdrCal 1: ExtOp ALUSelA ALUSelB=11 ALUOp=Add x: MemtoReg PCSrc 1: ALUSelA RegWr, ExtOp MemtoReg ALUSelB=11 ALUOp=Add x: PCSrc IorD LWwr Latch data read from memory in rt PCSrc=x ALUSelA=1 0 1 32 1 0 32 0 1 2 3 32 BrWr=0 32 lw or sw sw SWMem 1: ExtOp MemWr ALUSelA ALUSelB=11 ALUOp=Add x: PCSrc,RegDst MemtoReg MemWr=0 IRWr=0 32 RegDst=0 RegWr=1 Target Mux lw ALUSelA, IorD ALUSelB=11 ALUOp=Add x: MemtoReg PCSrc 1: ExtOp LWmem Rtype RExec 1: RegDst Ori OriExec ALUOp=Or 1: ALUSelA ALUSelB=11 x: MemtoReg IorD, PCSrc ALUSelA ALUSelB=01 ALUOp=Rtype x: PCSrc, IorD MemtoReg ExtOp Rs 32 Rt Rt 0 Rd 1 5 5 Zero ALU Mux Instruction Reg Ra Rb Rw busW busB 32 busA Mux Ideal Memory 32 Reg File 4 Mux WrAdr 32 Din Dout 32 LWwr 1: ALUSelA RegWr, ExtOp MemtoReg ALUSelB=11 ALUOp=Add x: PCSrc IorD Rfinish OriFinish ALUOp=Or x: IorD, PCSrc ALUSelB=11 1: ALUSelA RegWr ALUOp=Rtype 1: RegDst, RegWr ALUselA ALUSelB=01 x: IorD, PCSrc ExtOp 1 Mux 0 << 2 ALU Control Imm 16 Extend 32 ExtOp=1 35 EEL-4713 Ann Gordon - Ross 36 EEL-4713 Ann Gordon - Ross MemtoReg=1 ALUOp=Add ALUSelB=11 Putting it all together: Multiple Cycle Datapath Putting it all together: Control State Diagram Ifetch ALUOp=Add 1: PCWr, IRWr x: PCWrCond RegDst, Mem2R Others: 0s Rfetch/Decode ALUOp=Add 1: BrWr, ExtOp ALUSelB=10 x: RegDst, PCSrc IorD, MemtoReg Others: 0s BrComplete beq ALUOp=Sub ALUSelB=01 x: IorD, Mem2Reg RegDst, ExtOp 1: PCWrCond ALUSelA PCSrc PCWr IorD PC PCWrCond Zero MemWr 32 32 Rs 32 Rt Rt 0 Rd 1 5 5 0 1 32 PCSrc IRWr RegDst RegWr ALUSelA 1 0 32 0 1 2 3 32 BrWr 32 AdrCal Target Zero ALU 1: ExtOp ALUSelA ALUSelB=11 ALUOp=Add x: MemtoReg PCSrc Mux lw or sw sw SWMem 1: ExtOp MemWr ALUSelA ALUSelB=11 ALUOp=Add x: PCSrc,RegDst MemtoReg 32 32 0 1 RAdr Ra Rb Rw busW busB 32 busA lw ALUSelA, IorD ALUSelB=11 ALUOp=Add x: MemtoReg PCSrc 1: ExtOp LWmem Rtype Ori OriExec ALUOp=Or 1: ALUSelA ALUSelB=11 x: MemtoReg IorD, PCSrc Mux Instruction Reg RExec 1: RegDst 32 32 37 EEL-4713 Ann Gordon - Ross Note: there is a multiple-cycle delay path There is no register to save the results between: 2) Register Fetch: busA <- Reg[rs] ; busB <- Reg[rt] 3) R-type Execution: ALU output <- busA op busB 4) R-type Completion: Reg[rd] <- ALU output Mux Instruction Reg 32 Ideal Memory Reg File 4 WrAdr 32 Din Dout 32 ALUSelA ALUSelB=01 ALUOp=Rtype x: PCSrc, IorD MemtoReg ExtOp 1 Mux 0 Mux << 2 ALU Control LWwr Imm 16 Extend 32 ALUOp ALUSelB ExtOp MemtoReg 1: ALUSelA RegWr, ExtOp MemtoReg ALUSelB=11 ALUOp=Add x: PCSrc IorD Rfinish OriFinish ALUOp=Or x: IorD, PCSrc ALUSelB=11 1: ALUSelA RegWr ALUOp=Rtype 1: RegDst, RegWr ALUselA ALUSelB=01 x: IorD, PCSrc ExtOp 38 EEL-4713 Ann Gordon - Ross A Multiple Cycle Delay Path (Continue) Register is NOT needed to save the outputs of Register Fetch: IRWr = 0: busA and busB will not change after Register Fetch Register is NOT needed to save the outputs of R-type Execution: busA and busB will not change after Register Fetch Control signals ALUSelA, ALUSelB, and ALUOp will not change after R-type Execution Consequently ALU output will not change after R-type Execution In theory, you need a register to hold a signal value if: Register here to save outputs of RExec? Register here to save outputs of Rfetch? PCWr Rs Rt Rt 0 Rd 1 5 5 Ra Rb Rw busW busB 32 busA 32 0 1 ALUselA Zero 32 (1) The signal is computed in one clock cycle and used in another. (2) AND the inputs to the functional block that computes this signal can change before the signal is written into a state element. You can save a register if Cond 1 is true BUT Cond 2 is false: But in practice, this will introduce a multiple cycle delay path: - A logic delay path that takes multiple cycles to propagate from one storage element to the next storage element Mux ALU Reg File 4 0 1 2 3 32 1 Mux 0 39 EEL-4713 Ann Gordon - Ross Mux 32 ALUselB ALU Control ALUOp 40 EEL-4713 Ann Gordon - Ross Pros and Cons of a Multiple Cycle Delay Path A 3-cycle path example: IR (storage) -> Reg File Read -> ALU -> Reg File Write (storage) Advantages: Register savings We can share time among cycles: - If ALU takes longer than one cycle, still OK as long as the entire path takes less than 3 cycles to finish 0 1 32 Pros and Cons of a Multiple Cycle Delay Path (Continue) Disadvantage: Static timing analyzer, which ONLY looks at delay between two storage elements, will report this as a timing violation You have to ignore the static timing analyzer s warnings 0 1 Rs 32 Rt Zero 32 32 32 32 Rs Rt Zero 32 Mux Mux Mux Instruction Reg 5 5 Ra Rb Rw busA 5 5 Ra Rb Rw Rt 0 Rd 1 41 EEL-4713 Ann Gordon - Ross Mux Instruction Reg busA 32 ALU ALU Reg File 4 0 1 2 3 Rt 0 Rd 1 Reg File 4 0 1 2 3 32 32 busW busB 32 busW busB 32 1 Mux 0 ALUselB ALU Control 1 Mux 0 ALUselB 42 EEL-4713 Ann Gordon - Ross ALU Control Summary Disadvantages of the Single Cycle Processor Long cycle time Cycle time is too long for all instructions except the Load Multiple Cycle Processor: Divide the instructions into smaller steps Execute each step (instead of the entire instruction) in one cycle Do NOT confuse Multiple Cycle Processor with multiple cycle delay path Multiple Cycle Processor executes each instruction in multiple clock cycles Multiple Cycle Delay Path: a combinational logic path between two storage elements that takes more than one clock cycle to complete It is possible (desirable) to build a MC Processor without MCDP: Use a register to save a signal s value whenever a signal is generated in one clock cycle and used in another cycle later 43 EEL-4713 Ann Gordon - Ross Control logic Review of Finite State Machine (FSM) control From Finite State Diagrams to Microprogramming 44 EEL-4713 Ann Gordon - Ross Overview Control may be designed using one of several initial representations. The choice of sequence control, and how logic is represented, can then be determined independently; the control can then be implemented with one of several methods using a structured logic technique. Initial Representation Finite State Diagram Microprogram Initial Representation: Finite State Diagram 0 Ifetch 2 AdrCal ALUOp=Add 1: PCWr, IRWr x: PCWrCond RegDst, Mem2R Others: 0s 1 Rfetch/Decode ALUOp=Add 1: BrWr, ExtOp ALUSelB=10 x: RegDst, PCSrc IorD, MemtoReg Others: 0s 8 BrComplete beq ALUOp=Sub ALUSelB=01 x: IorD, Mem2Reg RegDst, ExtOp 1: PCWrCond ALUSelA PCSrc 1: ExtOp ALUSelA ALUSelB=11 ALUOp=Add x: MemtoReg PCSrc lw or sw sw lw Rtype RExec 5 SWMem 6 1: ExtOp MemWr ALUSelA ALUSelB=11 ALUOp=Add x: PCSrc,RegDst MemtoReg Ori 10 Sequencing Control Explicit Next State Function Logic Equations Microprogram counter + Dispatch ROMs Truth Tables ALUSelA, IorD ALUSelB=11 ALUOp=Add x: MemtoReg PCSrc 1: ExtOp LWmem 3 1: RegDst ALUSelA ALUSelB=01 ALUOp=Rtype x: PCSrc, IorD MemtoReg ExtOp OriExec ALUOp=Or 1: ALUSelA ALUSelB=11 x: MemtoReg IorD, PCSrc Logic Representation 11 7 Rfinish ALUOp=Rtype 1: RegDst, RegWr ALUselA ALUSelB=01 x: IorD, PCSrc ExtOp OriFinish 4 LWwr Implementation Technique PLA hardwired control ROM microprogrammed control 9: Jump See Fig C.3.1 1: ALUSelA RegWr, ExtOp MemtoReg ALUSelB=11 ALUOp=Add x: PCSrc IorD ALUOp=Or x: IorD, PCSrc ALUSelB=11 1: ALUSelA RegWr 45 EEL-4713 Ann Gordon - Ross 46 EEL-4713 Ann Gordon - Ross Sequencing Control: Explicit Next State Function Control Logic O u t p u t s Interface in detail Multicycle Datapath Inputs Opcode State Reg Next state number is encoded just like datapath controls 47 EEL-4713 Ann Gordon - Ross 48 EEL-4713 Ann Gordon - Ross Logic Representation: Logic Equations Next state from current state State 0 -> State1 State 1 -> S2, S6, S8, S10 State 2 -> S3, S5 State 3 -> State 4 State 4 ->State 0 State 5 -> State 0 State 6 -> State 7 State 7 -> State 0 State 8 -> State 0 State 9-> State 0 State 10 -> State 11 State 11 -> State 0 Alternatively, prior state & condition S4, S5, S7, S8, S9, S11 -> State0 State 0_____________ -> State 1 State 1 & op = lw|sw -> State 2 State2 & op = lw ____ -> State 3 State 3 ____________ -> State 4 State2 & op = sw ____ -> State 5 State 1 & op = R-type -> State 6 State 6 _____________-> State 7 State 1 & op = beq___ -> State 8 State2 & op = jmp ___-> State 9 State 1& op = ORi__ -> State 10 State 10 __________ -> State 11 See Fig. C.3.3 49 EEL-4713 Ann Gordon - Ross Implementation Technique: Programmed Logic Arrays Each output line: the logical OR of logical AND of input lines or their complement; AND minterms specified in top AND plane, OR sums specified in bottom OR plane Op5 Op4 Op3 Op2 Op1 Op0 S3 S2 S1 S0 0 = 0000 6 = 0110 1 = 0001 7 = 0111 2 = 0010 8 = 1000 3 = 0011 9 = 1001 4 = 0100 10 = 1010 5 = 0101 11 = 1011 50 EEL-4713 Ann Gordon - Ross R = 000000 beq = 000100 lw = 100011 sw = 101011 ori = 001011 jmp = 000010 Op=any S=0 Next=1 NS3 NS2 NS1 NS0 Implementation Technique: Programmed Logic Arrays Each output line the logical OR of logical AND of input lines or their complement: AND minterms specified in top AND plane, OR sums specified in bottom OR plane Multicycle Control Given numbers assigned to FSM, can in turn determine next state as function of inputs, including current state Turn these into Boolean equations for each bit of the next state lines Can implement easily using PLA Or ROM storing truth tables See Figs. C.3.6 and C.3.8 for tables showing outputs and next state as function of current state and opcode What if many more states, many more conditions? State machine gets too large; very large ROMs/PLAs What if need to add a state? Op5 Op4 Op3 Op2 Op1 Op0 S3 S2 S1 S0 0 = 0000 6 = 0110 1 = 0001 7 = 0111 2 = 0010 8 = 1000 3 = 0011 9 = 1001 4 = 0100 10 = 1010 5 = 0101 11 = 1011 51 EEL-4713 Ann Gordon - Ross lw = 100011 sw = 101011 R = 000000 ori = 001011 beq = 000100 jmp = 000010 NS3 NS2 NS1 NS0 May need to increase address for ROM, number of inputs for PLA gates 52 EEL-4713 Ann Gordon - Ross Next Iteration: Using Sequencer for Next State Before: Explicit Next State; Next try variation 1 step from right hand side Few sequential states in small FSM: suppose added floating point? Still need to go to non-sequential states: e.g., state 1 => 2, 6, 8, 10 Initial Representation Finite State Diagram Microprogram Sequencer-based control unit Control Logic Outputs Inputs Multicycle Datapath Sequencing Control Explicit Next State Function Logic Equations Microprogram counter + Dispatch ROMs Truth Tables 1 Logic Representation Adder State Reg Address Select Logic Implementation Technique PLA hardwired control ROM microprogrammed control Opcode 53 EEL-4713 Ann Gordon - Ross 54 EEL-4713 Ann Gordon - Ross A processor on its own Set state to 0 Dispatch (state 1 & 2) Incremented state number ( microPC ) and micro branches specify whether to increment or select another state based on opcode Sequencer-based control unit Control Logic Outputs Inputs Multicycle Datapath Sequencer block diagram Before: 6bit opcode + 4-bit state -> 4-bit NS Now: 4-bit state -> 2-bit AddrCtrl 0000 AddrCtrl=3 (fetch) 0001 AddrCtrl=1 (decode) 0010 AddrCtrl=2 (lw/sw) 0011 AddrCtrl=3 (lw) 0100 AddrCtrl=0 (lw) 0101 AddrCtrl=0 (sw) 0110 AddrCtrl=3 (r-type) 0111 AddrCtrl=0 (r-type) 1000 AddrCtrl=0 (branch) 1010 AddrCtrl=3 (ori) 1011 AddrCtrl=0 (ori) Dispatch ROM 1 (Indexed by opcode) lw -> 0010 sw -> 0010 R-type -> 0110 ori -> 1010 branch -> 1000 ROM2: lw -> 0011 sw -> 0101 1 Adder State Reg Address Select Logic Opcode AddrCtrl control for select logic 0: reset state register (next instruction) 1: select next using next-state ROM for state 1 2: select next using next-state ROM for state 2 3: increment state Fig. C.4.2 55 EEL-4713 Ann Gordon - Ross 56 EEL-4713 Ann Gordon - Ross Initial Representation: Finite State Diagram 0 Ifetch 2 AdrCal ALUOp=Add 1: PCWr, IRWr x: PCWrCond RegDst, Mem2R Others: 0s Next Iteration: Using Microprogram for Representation Initial Representation Finite State Diagram Microprogram 1 Rfetch/Decode ALUOp=Add 1: BrWr, ExtOp ALUSelB=10 x: RegDst, PCSrc IorD, MemtoReg Others: 0s 8 BrComplete beq ALUOp=Sub ALUSelB=01 x: IorD, Mem2Reg RegDst, ExtOp 1: PCWrCond ALUSelA PCSrc 1: ExtOp ALUSelA ALUSelB=11 ALUOp=Add x: MemtoReg PCSrc lw or sw sw Sequencing Control Explicit Next State Function Logic Equations Microprogram counter + Dispatch ROMs Truth Tables lw Rtype RExec 5 SWMem 6 1: ExtOp MemWr ALUSelA ALUSelB=11 ALUOp=Add x: PCSrc,RegDst MemtoReg Ori 10 ALUSelA, IorD ALUSelB=11 ALUOp=Add x: MemtoReg PCSrc 1: ExtOp LWmem 3 1: RegDst ALUSelA ALUSelB=01 ALUOp=Rtype x: PCSrc, IorD MemtoReg ExtOp OriExec ALUOp=Or 1: ALUSelA ALUSelB=11 x: MemtoReg IorD, PCSrc Logic Representation Implementation Technique PLA hardwired control ROM microprogrammed control 11 7 Rfinish ALUOp=Rtype 1: RegDst, RegWr ALUselA ALUSelB=01 x: IorD, PCSrc ExtOp OriFinish 4 LWwr 9: Jump See Fig C.3.1 1: ALUSelA RegWr, ExtOp MemtoReg ALUSelB=11 ALUOp=Add x: PCSrc IorD ALUOp=Or x: IorD, PCSrc ALUSelB=11 1: ALUSelA RegWr ROM can be thought of as a sequence of control words Control word can be thought of as instruction: microinstruction 57 EEL-4713 Ann Gordon - Ross 58 EEL-4713 Ann Gordon - Ross Microprogramming Control is the hard part of processor design Datapath is fairly regular and well-organized Memory is highly regular Control is irregular and global Microprogramming: -- A particular strategy for implementing the control unit of a processor by "programming" at the level of register transfer operations Microarchitecture: -- Logical structure and functional capabilities of the hardware as seen by the microprogrammer Macroinstruction Interpretation User program plus Data this can change! Main Memory ADD SUB AND . . . DATA execution unit CPU control memory one of these is mapped into one of these AND microsequence e.g., Fetch Calc Operand Addr Fetch Operand(s) Calculate Save Answer(s) 59 EEL-4713 Ann Gordon - Ross 60 EEL-4713 Ann Gordon - Ross Microprogramming Pros and Cons Ease of design Flexibility Easy to adapt to changes in organization, timing, technology Can make changes late in design cycle, or even in the field Can implement very powerful instruction sets (just more control memory) Generality Can implement multiple instruction sets on same machine. Can tailor instruction set to application. Compatibility Many organizations, same instruction set Costly to implement Slow 61 EEL-4713 Ann Gordon - Ross Summary: Multicycle Control Microprogramming and hardwired control have many similarities, perhaps biggest difference is initial representation and ease of change of implementation, with ROM generally being easier than PLA Initial Representation Finite State Diagram Microprogram Sequencing Control Explicit Next State Function Logic Equations Microprogram counter + Dispatch ROMs Truth Tables Logic Representation Implementation Technique PLA hardwired control ROM microprogrammed control 62 EEL-4713 Ann Gordon - Ross ...
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