Lec7-mpy-shift - EEL-4713 Ann Gordon-Ross.1 EEL-4713...

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Unformatted text preview: EEL-4713 Ann Gordon-Ross.1 EEL-4713 Computer Architecture Multipliers and shifters EEL-4713 Ann Gordon-Ross.2 Outline Multiplication and shift registers Chapter 3, section 3.4 Next lecture Division, floating-point 3.5 3.6 EEL-4713 Ann Gordon-Ross.3 Deriving requirements of ALU Start with instruction set architecture: must be able to do all operations in ISA Tradeoffs of cost and speed based on frequency of occurrence, hardware budget MIPS ISA EEL-4713 Ann Gordon-Ross.4 MIPS arithmetic instructions Instruction Example Meaning Comments add add $1,$2,$3 $1 = $2 + $3 3 operands; exception possible subtract sub $1,$2,$3 $1 = $2 $3 3 operands; exception possible add immediate addi $1,$2,100 $1 = $2 + 100 + constant; exception possible add unsigned addu $1,$2,$3 $1 = $2 + $3 3 operands; no exceptions subtract unsigned subu $1,$2,$3 $1 = $2 $3 3 operands; no exceptions add imm. unsign. addiu $1,$2,100 $1 = $2 + 100 + constant; no exceptions multiply mult $2,$3 Hi, Lo = $2 x $3 64-bit signed product multiply unsigned multu$2,$3 Hi, Lo = $2 x $3 64-bit unsigned product divide div $2,$3 Lo = $2 $3, Lo = quotient, Hi = remainder Hi = $2 mod $3 divide unsigned divu $2,$3 Lo = $2 $3, Unsigned quotient & remainder Hi = $2 mod $3 Move from Hi mfhi $1 $1 = Hi Used to get copy of Hi Move from Lo mflo $1 $1 = Lo Used to get copy of Lo EEL-4713 Ann Gordon-Ross.5 MIPS ALU requirements Add, AddU, Sub, SubU, AddI, AddIU => 2 ` s complement adder with overflow detection & inverter SLTI, SLTIU (set less than) => 2 ` s complement adder with inverter, check sign bit of result BEQ, BNE (branch on equal or not equal) => 2 ` s complement adder with inverter, check if result = 0 And, Or, AndI, OrI => Logical AND, logical OR ALU from last lecture supports these ops EEL-4713 Ann Gordon-Ross.6 Additional MIPS ALU requirements Xor, Nor, XorI => Logical XOR, logical NOR Sll, Srl, Sra => Need left shift, right shift, right shift arithmetic by 0 to 31 bits Mult, MultU, Div, DivU => Need 32-bit multiply and divide, signed and unsigned EEL-4713 Ann Gordon-Ross.7 MULTIPLY (unsigned) Paper and pencil example (unsigned): Multiplicand 1000 Multiplier 1001 1000 0000 0000 1000 Product 01001000 m bits x n bits = m+n bit product Binary makes it easy: 0 => place 0 ( 0 x multiplicand) 1 => place a copy ( 1 x multiplicand) 4 versions of multiply hardware & algorithm: successive refinement EEL-4713 Ann Gordon-Ross.8 Unsigned Combinational Multiplier: A * B Stage i accumulates A * 2 i if B i == 1 Q: How much hardware for 32 bit multiplier? Critical path? B 0 A 0 A 1 A 2 A 3 A 0 A 1 A 2 A 3 A 0 A 1 A 2 A 3 B 1 B 2 B 3 P 0 P 1 P 2 P 3 P 4 P 5 P 6 P 7 0 0 0 0 Bi=0 do not add Bi=1 add Ai Prev Bj Ai+Prev Cout Control bits A 0 A 1 A 2 A 3 EEL-4713 Ann Gordon-Ross.9 How does it work?...
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Lec7-mpy-shift - EEL-4713 Ann Gordon-Ross.1 EEL-4713...

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