Lec10-pipeline - EEL-4713 Ann Gordon-Ross 1 EEL-4713C...

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Unformatted text preview: EEL-4713 Ann Gordon-Ross 1 EEL-4713C Computer Architecture Designing a Pipelined Processor EEL-4713 Ann Gordon-Ross 2 Outline Introduction to the pipelined datapath/control Key concepts and examples Beginning with multi-cycle datapath Reading: 4.5-4.9 EEL-4713 Ann Gordon-Ross 3 Recap: Multiple Cycle Implementation Break the instruction into smaller steps Execute each step (instead of the entire instruction) in one cycle - Strive to keep steps with similar length Instructions take multiple cycles to execute Only one instruction uses the datapath at any given cycle Pipelining Goal: improve performance by having multiple instructions in the datapath at any given cycle EEL-4713 Ann Gordon-Ross 4 Pipelining is Natural! Laundry Example Alice, Bob, Charlie, and Debbie each have one load of clothes to wash, dry, and fold Washer takes 30 minutes Drier takes 30 minutes l Folder z takes 30 minutes l Stasher z takes 30 minutes to put clothes into drawers A B C D EEL-4713 Ann Gordon-Ross 5 Sequential Laundry Sequential laundry takes 8 hours for 4 loads 30 T a s k O r d e r B C D A Time 30 30 30 30 30 30 30 30 30 30 30 30 30 30 30 6 PM 7 8 9 10 11 12 1 2 AM EEL-4713 Ann Gordon-Ross 6 Pipelined Laundry: Start work ASAP Pipelined laundry takes 3.5 hours for 4 loads! T a s k O r d e r 12 2 AM 6 PM 7 8 9 10 11 1 Time B C D A 30 30 30 30 30 30 30 EEL-4713 Ann Gordon-Ross 7 Pipelining Lessons Pipelining doesn ` t help latency of single task, it helps throughput of entire workload Multiple tasks operating simultaneously using different resources Potential speedup = Number of pipe stages Also: Pipeline rate limited by slowest pipeline stage Unbalanced lengths of pipe stages reduces speedup Time to l fill z pipeline and time to l drain z it reduces speedup Dependences - stalls 6 PM 7 8 9 Time B C D A 30 30 30 30 30 30 30 T a s k O r d e r EEL-4713 Ann Gordon-Ross 8 Why Pipeline? Suppose we execute 100 instructions Single Cycle Machine, 220MHz 4.5 ns/cycle x 1 CPI x 100 inst = 450 ns Multicycle Machine, 1GHz, average CPI 4.6 1 ns/cycle x 4.6 CPI x 100 inst = 460 ns Ideal pipelined machine, 1GHz 1 ns/cycle x (1 CPI x 100 inst + 4 cycle drain) = 104 ns EEL-4713 Ann Gordon-Ross 9 Datapath: from multicycle to pipelined Key approach: Begin by considering each cycle a pipeline stage Add registers between consecutive stages to store data and control bits flowing from one stage to the next Add logic to deal with l hazards z- Ensure functional units are not used by more than one stage at the same time - Ensure producer/consumer dependences are not violated Example: load instruction EEL-4713 Ann Gordon-Ross 10 Timing Diagram of a Load Instruction Clk PC Rs, Rt, Rd, Op, Func Clk-to-Q ALUctr Instruction Memory Access Time Old Value New Value RegWr Old Value New Value Delay through Control Logic busA Register File Access Time Old Value New Value busB ALU Delay...
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This note was uploaded on 01/09/2012 for the course EEL 4713 taught by Professor Staff during the Spring '11 term at University of Florida.

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Lec10-pipeline - EEL-4713 Ann Gordon-Ross 1 EEL-4713C...

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