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Lec11-pipe-hazard - Outline Announcements Introduction to...

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EEL4713C Ann Gordon-Ross .1 EEL-4713C Computer Architecture Pipelined Processor - Hazards EEL4713C Ann Gordon-Ross .2 Outline & Announcements ° Introduction to Hazards ° Forwarding ° 1 cycle Load Delay ° 1 cycle Branch Delay ° What makes pipelining hard EEL4713C Ann Gordon-Ross .3 Pipelining – dealing with hazards ° Limits to pipelining: Hazards prevent next instruction from executing during its designated clock cycle structural hazards : HW cannot support this combination of instructions data hazards : instruction depends on result of prior instruction still in the pipeline control hazards : pipelining of branches & other instructions that change the PC ° Common solution is to stall the pipeline until the hazard is resolved, inserting one or more bubbles in the pipeline EEL4713C Ann Gordon-Ross .4 Mem Single Memory is a Structural Hazard I n s t r. O r d e r Time (clock cycles) Load Instr 1 Instr 2 Instr 3 Instr 4 ALU Mem Reg Mem Reg ALU Mem Reg Mem Reg ALU Mem Reg Mem Reg ALU Reg Mem Reg ALU Mem Reg Mem Reg
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EEL4713C Ann Gordon-Ross .5 Option 1: Stall to resolve Memory Structural Hazard I n s t r. O r d e r Time (clock cycles) Load Instr 1 Instr 2 Instr 3 (stall) Instr 4 ALU Mem Reg Mem Reg ALU Mem Reg Mem Reg ALU Mem Reg Mem Reg bubble ALU Mem Reg Mem Reg ALU Mem Reg Mem Reg EEL4713C Ann Gordon-Ross .6 Option 2: Duplicate to Resolve Structural Hazard I n s t r. O r d e r Time (clock cycles) Load Instr 1 Instr 2 Instr 3 Instr 4 ALU Im Reg Dm Reg ALU Im Reg Dm Reg ALU Im Reg Dm Reg Im ALU Reg Dm Reg ALU Im Reg Dm Reg Separate Instruction Cache (Im) & Data Cache (Dm) EEL4713C Ann Gordon-Ross .7 Data Hazard on r1 add r1 ,r2,r3 sub r4, r1 ,r3 and r6, r1 ,r7 or r8, r1 ,r9 xor r10, r1 ,r11 EEL4713C Ann Gordon-Ross .8 Data Hazard on r1: I n s t r. O r d e r Time (clock cycles) add r1 ,r2,r3 sub r4, r1 ,r3 and r6, r1 ,r7 or r8, r1 ,r9 xor r10, r1 ,r11 IF ID/RF EX MEM WB ALU Im Reg Dm Reg ALU Im Reg Dm Reg ALU Im Reg Dm Reg Im ALU Reg Dm Reg ALU Im Reg Dm Reg Dependencies backwards in time are hazards
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EEL4713C Ann Gordon-Ross .9 sub r4, r1 ,r3 and r6, r1 ,r7 or r8, r1 ,r9 xor r10, r1 ,r11 Option1: HW Stalls to Resolve Data Hazard I n s t r. O r d e r Time (clock cycles) add r1 ,r2,r3 IF ID/RF EX MEM WB ALU Im Reg Dm Reg ALU Im Reg Dm Im bubble bubble bubble ALU Reg Dm Reg ALU Im Reg Im Reg EEL4713C Ann Gordon-Ross .10 But recall how the control logic works ° The Main Control generates the control signals during Reg/Dec Control signals for Exec (ExtOp, ALUSrc, ...) are used 1 cycle later Control signals for Mem (MemWr Branch) are used 2 cycles later Control signals for Wr (MemtoReg MemWr) are used 3 cycles later IF/ID Register ID/Ex Register Ex/Mem Register Mem/Wr Register Reg/Dec Exec Mem ExtOp ALUOp RegDst ALUSrc Branch MemWr MemtoReg RegWr Main Control ExtOp ALUOp RegDst ALUSrc MemtoReg RegWr MemtoReg RegWr MemtoReg RegWr Branch MemWr Branch MemWr Wr EEL4713C Ann Gordon-Ross .11 Option 1: HW stalls pipeline I n s t r.
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