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Lec12-cache - EEL-4713 Computer Architecture Memory...

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EEL-4713 Ann Gordon-Ross 1 EEL-4713 Computer Architecture Memory hierarchies
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EEL-4713 Ann Gordon-Ross 2 The Motivation for Caches ° Motivation: Large memories (DRAM) are slow Small memories (SRAM) are fast ° Make the average access time small by: Servicing most accesses from a small, fast memory. ° Reduce the bandwidth required of the large memory Processor Memory System Cache DRAM
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EEL-4713 Ann Gordon-Ross 3 Outline of Today’s Lecture ° Introduction to Memory Hierarchies & caches ° Cache write and replacement policies
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EEL-4713 Ann Gordon-Ross 4 *An Expanded View of the Memory System Control Datapath Memory Processor M e m o r y Memory Memory M e m o r y Fastest Slowest Smallest Biggest Highest Lowest Speed: Size: Cost:
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EEL-4713 Ann Gordon-Ross 5 The Principle of Locality Address Space 0 memsize Probability of reference What are the principles of Locality?
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EEL-4713 Ann Gordon-Ross 6 The Principle of Locality ° The Principle of Locality: Program access a relatively small portion of the address space at any instant of time. Example: 90% of time in 10% of the code ° Two Different Types of Locality: Temporal Locality (Locality in Time): If an item is referenced, it will tend to be referenced again soon. Spatial Locality (Locality in Space): If an item is referenced, items whose addresses are close by tend to be referenced soon. Address Space 0 memsize Probability of reference
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EEL-4713 Ann Gordon-Ross 7 Memory Hierarchy: Principles of Operation ° 2-level hierarchy example ° At any given time, data is copied between only 2 adjacent levels: Upper Level (Cache) : the one closer to the processor - Smaller, faster, and uses more expensive technology Lower Level (Memory): the one further away from the processor - Bigger, slower, and uses less expensive technology ° Block: The minimum unit of information that can either be present or not present in the two-level hierarchy Lower Level (Memory) Upper Level (Cache) To Processor From Processor Blk X Blk Y
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EEL-4713 Ann Gordon-Ross 8 Memory Hierarchy: Terminology ° Hit: data appears in some block in the upper level (example: Block X) Hit Rate: the fraction of memory accesses found in the upper level Hit Time: Time to access the upper level which consists of RAM access time + Time to determine hit/miss ° Miss: data needs to be retrieved from a block in the lower level (Block Y) Miss Rate = 1 - (Hit Rate) Miss Penalty = Time to replace a block in the upper level + Time to deliver the block the processor ° Hit Time << Miss Penalty Lower Level (Memory) Upper Level (Cache) To Processor From Processor Blk X Blk Y
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EEL-4713 Ann Gordon-Ross 9 Basic Terminology: Typical Values Typical Values Block (line) size 4 - 128 bytes Hit time 1 - 4 cycles Miss penalty 10 - 100 cycles (and increasing) Miss rate 1% - 20% Cache Size 64 KB - 8 MB
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EEL-4713 Ann Gordon-Ross 10 How Do Caches Work?
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