Unformatted text preview: VHDL Math Tricks of the Trade
by Jim Lewis Director of Training, SynthWorks Design Inc [email protected] http://www.SynthWorks.com Lewis Copyright © 2003 SynthWorks Design Inc. All Rights Reserved. MAPLD 2003 VHDL Math Tricks of the Trade SynthWorks VHDL is a strongly typed language. Success in VHDL depends on understanding the types and overloaded operators provided by the standard and numeric packages. The paper gives a short tutorial on: • VHDL Types & Packages • Strong Typing Rules • Converting between Std_logic_vector, unsigned & signed • Ambiguous Expressions • Arithmetic Coding Considerations • Math Tricks
Lewis
Copyright © 2003 SynthWorks Design Inc. All Rights Reserved. MAPLD 2003 P2 Common VHDL Types
TYPE
std_ulogic std_ulogic_vector std_logic std_logic_vector unsigned signed boolean character string integer real time
Lewis SynthWorks
Origin
std_logic_1164 std_logic_1164 std_logic_1164 std_logic_1164 numeric_std, std_logic_arith numeric_std, std_logic_arith standard standard standard standard standard standard
MAPLD 2003 P3 Value
'U', 'X', '0', '1', 'Z', 'W', 'L', 'H', '' array of std_ulogic resolved std_ulogic array of std_logic array of std_logic array of std_logic true, false 191 / 256 characters array of character (231 1) to (231  1) 1.0E38 to 1.0E38 1 fs to 1 hr
Copyright © 2003 SynthWorks Design Inc. All Rights Reserved. Packages for Numeric Operations
● SynthWorks numeric_std  IEEE standard ● Defines types signed, unsigned ● Defines arithmetic, comparison, and logic operators for these types std_logic_arith  Synopsys, a defacto industry standard ● Defines types signed, unsigned ● Defines arithmetic, and comparison operators for these types std_logic_unsigned  Synopsys, a defacto industry standard ● Defines arithmetic and comparison operators for std_logic_vector ● ● Recommendation: Use numeric_std for new designs Ok to use std_logic_unsigned with numeric_std*
* Currently, IEEE 1076.3 plans to have a numeric package that permits unsigned math with std_logic_vector
Lewis
Copyright © 2003 SynthWorks Design Inc. All Rights Reserved. MAPLD 2003 P4 Packages for Numeric Operations
● SynthWorks Using IEEE Numeric_Std
library ieee ; library ieee ; use ieee.std_logic_1164.all ; use ieee.std_logic_1164.all ; use ieee.numeric_std.all ; numeric_std use ieee.numeric_std.all ; Recommendation: Recommendation: Use numeric_std for new designs Use numeric_std for new designs Use numeric_std or Use numeric_std or std_logic_arith,, but std_logic_arith but never both never both ● Using Synopsys Std_Logic_Arith
library ieee ; library ieee ; use ieee.std_logic_1164.all ; use ieee.std_logic_1164.all ; use ieee.std_logic_arith.all ; std_logic_arith use ieee.std_logic_arith.all ; use ieee.std_logic_unsigned.all ; use ieee.std_logic_unsigned.all ; Recommendation, if you use Synopsys Packages: Recommendation, if you use Synopsys Packages: Use std_logic_arith for numeric operations Use std_logic_arith for numeric operations Use std_logic_unsigned only for counters and testbenches Use std_logic_unsigned only for counters and testbenches Don't use the package std_logic_signed. Don't use the package std_logic_signed. Lewis Copyright © 2003 SynthWorks Design Inc. All Rights Reserved. MAPLD 2003 P5 Unsigned and Signed Types
● SynthWorks Used to represent numeric values: TYPE unsigned signed Value N 0 to 2N  1 (N1) (N1)  2(N1) to 2(N1)  1 Notes 2's Complement number ● Usage similar to std_logic_vector:
signal A_unsigned signal B_signed signal C_slv ... : unsigned(3 downto 0) ; : signed (3 downto 0) ; : std_logic_vector (3 downto 0) ;
= 15 decimal = 15 decimal = 1 decimal = 1 decimal = 15 decimal only if using = 15 decimal only if using std_logic_unsigned std_logic_unsigned
MAPLD 2003 P6 A_unsigned <= "1111" ; B_signed C_slv
Lewis <= "1111" ; <= "1111" ; Copyright © 2003 SynthWorks Design Inc. All Rights Reserved. Unsigned and Signed Types
● SynthWorks Type definitions identical to std_logic_vector
type UNSIGNED is array (natural range <>) of std_logic; type SIGNED is array (natural range <>) of std_logic; ● ● ● How are the types distinguished from each other? How do these generate unsigned and signed arithmetic? For each operator, a unique function is called
function "+" (L, R: signed) return signed; function "+" (L, R: unsigned) return unsigned ; ● This feature is called Operator Overloading: ● An operator symbol or subprogram name can be used more than once as long as calls are differentiable.
Copyright © 2003 SynthWorks Design Inc. All Rights Reserved. Lewis MAPLD 2003 P7 Overloading Basics
● SynthWorks Simplified view of overloading provided by VHDL packages
Operator Operator Logic Logic Numeric Left Left TypeA TypeA Array Array Integer Right Right TypeA TypeA Array Integer Array Result Result TypeA TypeA Array1 Array1 Array1 Notes: Notes: Array = Array = TypeA = TypeA = unsigned, signed, std_logic_vector2 unsigned, signed, std_logic_vector2 boolean, std_logic, std_ulogic, bit_vector boolean, std_logic, std_ulogic, bit_vector std_logic_vector, std_ulogic_vector, std_logic_vector, std_ulogic_vector, signed3, unsigned3 signed3, unsigned3 Array and TypeA types used in an expression must be the same. Array and TypeA types used in an expression must be the same. 1) for comparison operators the result is boolean 2) only for std_logic_unsigned. 3) only for numeric_std and not std_logic_arith
● For a detailed view of VHDL's overloading, get the VHDL Types and Operators Quick Reference card at: http://www.SynthWorks.com/papers
Copyright © 2003 SynthWorks Design Inc. All Rights Reserved. Lewis MAPLD 2003 P8 Overloading Examples
Signal Signal Signal Signal Signal Signal signal signal ... ... SynthWorks A_uv, B_uv, C_uv, D_uv, E_uv : unsigned(7 downto 0) ; A_uv, B_uv, C_uv, D_uv, E_uv : unsigned(7 downto 0) ; R_sv, S_sv, T_sv, U_sv, V_sv : signed(7 downto 0) ; R_sv, S_sv, T_sv, U_sv, V_sv : signed(7 downto 0) ; J_slv, K_slv, L_slv : std_logic_vector(7 downto 0) ; J_slv, K_slv, L_slv : std_logic_vector(7 downto 0) ; Y_sv : signed(8 downto 0) ; Y_sv : signed(8 downto 0) ;  Permitted  Permitted A_uv <= B_uv + C_uv ; A_uv <= B_uv + C_uv ; D_uv <= B_uv + 1 ; D_uv <= B_uv + 1 ; E_uv <= 1 + C_uv; E_uv <= 1 + C_uv; R_sv R_sv U_sv U_sv V_sv V_sv <= <= <= <= <= <= S_sv + T_sv ; S_sv + T_sv ; S_sv + 1 ; S_sv + 1 ; 1 + T_sv; 1 + T_sv;  Unsigned + Unsigned = Unsigned  Unsigned + Unsigned = Unsigned  Unsigned + Integer = Unsigned  Unsigned + Integer = Unsigned  Integer + Unsigned = Unsigned  Integer + Unsigned = Unsigned Signed Signed Signed Signed Integer Integer + + + + + + Signed Signed Integer Integer Signed Signed = = = = = = Signed Signed Signed Signed Signed Signed J_slv <= K_slv + L_slv ; J_slv <= K_slv + L_slv ; Lewis  if using std_logic_unsigned  if using std_logic_unsigned Illegal Cannot mix different array types Illegal Cannot mix different array types Solution persented later in type conversions Solution persented later in type conversions Y_sv <= A_uv  B_uv ;  want signed result Y_sv <= A_uv  B_uv ;  want signed result
Copyright © 2003 SynthWorks Design Inc. All Rights Reserved. MAPLD 2003 P9 Strong Typing Implications
● ● SynthWorks Size and type of target (left) = size and type of expression (right) Each operation returns a result that has a specific size based on rules of the operation. The table below summarizes these rules.
Operation Y <= "10101010" ; Y <= X"AA" ; Y <= A ; Y <= A and B ; W <= A > B ; Y <= A + B ; Y <= A + 10 ; V <= A * B ; Size of Y = Size of Expression number of digits in literal 4 * (number of digits) A'Length = Length of array A A'Length = B'Length Boolean Maximum (A'Length, B'Length) A'Length A'Length + B'Length Some think VHDL is difficult because of strong typing Master the above simple rules and it is easy
Lewis
Copyright © 2003 SynthWorks Design Inc. All Rights Reserved. MAPLD 2003 P10 Strong Typing Implications
signal A8, B8, Result8 signal Result9 signal Result7 ...  Simple Addition, no Result8 <= A8 + B8 ; : : : unsigned(7 unsigned(8 unsigned(6 downto downto downto 0) 0) 0) SynthWorks
; ; ; carry out  Carry Out in result Result9 <= ('0' & A8) + ('0' & B8) ;  For smaller result, slice input arrays Result7 <= A8(6 downto 0) + B8(6 downto 0) ; Strong Typing = Strong Error Checking Built into the Compiler This means less debugging. Without VHDL, you better have a good testbench and lots of time to catch your errors.
Lewis
Copyright © 2003 SynthWorks Design Inc. All Rights Reserved. MAPLD 2003 P11 Type Conversions
● ● SynthWorks VHDL is dependent on overloaded operators and conversions What conversion functions are needed? ● Signed & Unsigned (elements) <=> Std_Logic
● ● ● Signed & Unsigned Signed & Unsigned Std_Logic_vector Automatic Type Conversion Conversion by Type Casting <=> Std_Logic_Vector <=> Integer <=> Integer ● VHDL BuiltIn Conversions
● ● ● Conversion functions located in Numeric_Std Lewis Copyright © 2003 SynthWorks Design Inc. All Rights Reserved. MAPLD 2003 P12 Automatic Type Conversion: Unsigned, Signed <=> Std_Logic
● SynthWorks Two types convert automatically when both are subtypes of the same type.
subtype std_logic is resolved std_ulogic ; subtype std_logic is resolved std_ulogic ;
● Converting between std_ulogic and std_logic is automatic ● Elements of Signed, Unsigned, and std_logic_vector = std_logic ● Elements of these types convert automatically to std_ulogic or std_logic
A_sl A_sl B_sul L_uv(0) M_slv(2) <= <= <= <= <= J_uv(0) ; J_uv(0) ; K_sv(7) ; C_sl ; N_sv(2) ; Legal Assignments Implication: Y_sl <= Y_sl <= A_sl and B_sul and A_sl and B_sul and J_uv(2) and K_sv(7) and M_slv(2); J_uv(2) and K_sv(7) and M_slv(2);
MAPLD 2003 P13 Lewis Copyright © 2003 SynthWorks Design Inc. All Rights Reserved. SynthWorks Type Casting: Unsigned, Signed <=> Std_Logic_Vector
● Use type casting to convert equal sized arrays when:
● ● Elements have a common base type (i.e. std_logic) Indices have a common base type (i.e. Integer) ● Unsigned, Signed < => Std_Logic_Vector
A_slv A_slv C_slv C_slv G_uv J_sv <= <= <= <= <= <= std_logic_vector( std_logic_vector( std_logic_vector( std_logic_vector( unsigned( H_slv ) signed( K_slv ) B_uv B_uv D_sv D_sv ; ; ); ); ); ); ● Motivation, Unsigned  Unsigned = Signed?
signal X_uv, Y_uv signal X_uv, Y_uv signal Z_sv signal Z_sv ... ... Z_sv <= signed('0' Z_sv <= signed('0' : unsigned (6 downto 0) ; : unsigned (6 downto 0) ; : signed (7 downto 0) ; : signed (7 downto 0) ; & X_uv)  signed('0' & Y_uv) ; & X_uv)  signed('0' & Y_uv) ;
MAPLD 2003 P14 Lewis Copyright © 2003 SynthWorks Design Inc. All Rights Reserved. Numeric_Std Conversions: Unsigned, Signed <=> Integer
● SynthWorks Converting to and from integer requires a conversion function. ● Unsigned, Signed => Integer
Unsigned_int Unsigned_int Signed_int Signed_int
● <= <= <= <= TO_INTEGER ( A_uv ) ; TO_INTEGER ( A_uv ) ; TO_INTEGER ( B_sv ) ; TO_INTEGER ( B_sv ) ; Integer => Unsigned, Signed
<= <= <= <= TO_UNSIGNED ( Unsigned_int, 8 ) ; TO_UNSIGNED ( Unsigned_int, 8 ) ; TO_SIGNED ( Signed_int, 8 ) ; TO_SIGNED ( Signed_int, 8 ) ; C_uv C_uv D_sv D_sv
● Array Array width = 8 width = 8 Motivation (indexing an array of an array):
Data_slv <= Data_slv <= ROM( ROM( TO_INTEGER( Addr_uv) ) ; TO_INTEGER( Addr_uv) ) ; signal signal signal signal signal signal signal signal
Lewis A_uv, C_uv A_uv, C_uv Unsigned_int Unsigned_int B_sv, D_sv B_sv, D_sv Signed_int Signed_int : : : : : : : : unsigned (7 downto 0) ; unsigned (7 downto 0) ; integer range 0 to 255 ; integer range 0 to 255 ; signed( 7 downto 0) ; signed( 7 downto 0) ; integer range 128 to 127; integer range 128 to 127;
Copyright © 2003 SynthWorks Design Inc. All Rights Reserved. MAPLD 2003 P15 Std_Logic_Arith Conversions: Unsigned, Signed <=> Integer
● SynthWorks Converting to and from integer requires a conversion function. ● Unsigned, Signed => Integer
Unsigned_int Unsigned_int Signed_int Signed_int
● <= Conv_INTEGER ( A_uv ) ; <= Conv_INTEGER ( A_uv ) ; <= Conv_INTEGER ( B_sv ) ; <= Conv_INTEGER ( B_sv ) ; Integer => Unsigned, Signed
<= Conv_UNSIGNED ( Unsigned_int, 8 ) ; <= Conv_UNSIGNED ( Unsigned_int, 8 ) ; <= Conv_SIGNED ( Signed_int, 8 ) ; <= Conv_SIGNED ( Signed_int, 8 ) ; C_uv C_uv D_sv D_sv
● Array Array width = 8 width = 8 Motivation (indexing an array of an array):
Data_slv <= Data_slv <= ROM( Conv_INTEGER( Addr_uv) ) ; ROM( Conv_INTEGER( Addr_uv) ) ; signal signal signal signal signal signal signal signal
Lewis A_uv, C_uv A_uv, C_uv Unsigned_int Unsigned_int B_sv, D_sv B_sv, D_sv Signed_int Signed_int : : : : : : : : unsigned (7 downto 0) ; unsigned (7 downto 0) ; integer range 0 to 255 ; integer range 0 to 255 ; signed( 7 downto 0) ; signed( 7 downto 0) ; integer range 128 to 127; integer range 128 to 127;
Copyright © 2003 SynthWorks Design Inc. All Rights Reserved. MAPLD 2003 P16 Std_Logic_Vector <=> Integer
● ● SynthWorks Converting between std_logic_vector and integer is a two step process: Numeric_Std:
Unsigned_int <= Unsigned_int <= Signed_int <= Signed_int <= Std_Logic_Vector => Integer
to_integer( to_integer( to_integer( to_integer( unsigned( A_slv )); unsigned( A_slv )); signed( B_slv )); signed( B_slv )); ● Numeric_Std:
C_slv C_slv D_slv D_slv Integer => Std_Logic_Vector <= std_logic_vector( to_unsigned( Unsigned_int, 8 )); <= std_logic_vector( to_unsigned( Unsigned_int, 8 )); <= std_logic_vector( to_signed( Signed_int, 8 )); <= std_logic_vector( to_signed( Signed_int, 8 )); signal signal signal signal signal signal signal signal
Lewis A_slv, C_slv A_slv, C_slv Unsigned_int Unsigned_int B_slv, D_slv B_slv, D_slv Signed_int Signed_int : : : : : : : : std_logic_vector (7 downto 0) ; std_logic_vector (7 downto 0) ; integer range 0 to 255 ; integer range 0 to 255 ; std_logic_vector( 7 downto 0) ; std_logic_vector( 7 downto 0) ; integer range 128 to 127; integer range 128 to 127;
MAPLD 2003 P17 Copyright © 2003 SynthWorks Design Inc. All Rights Reserved. Ambiguous Expressions
● SynthWorks An expression / statement is ambiguous if more than one operator symbol or subprogram can match its arguments. Std_Logic_Arith defines the following two functions:
function "+" (L, R: SIGNED) return SIGNED; function "+" (L, R: SIGNED) return SIGNED; function "+" (L: SIGNED; R: UNSIGNED) return SIGNED; function "+" (L: SIGNED; R: UNSIGNED) return SIGNED; ● ● The following expression is ambiguous and an error:
Z_sv Z_sv <= <= A_sv A_sv + "1010" ; + "1010" ; Is "1010" Signed or Unsigned Is "1010" Signed or Unsigned
"1010" =
● 6 or 10 Issues typically only arise when using literals. ● How do we solve this problem? Lewis Copyright © 2003 SynthWorks Design Inc. All Rights Reserved. MAPLD 2003 P18 Std_Logic_Arith: Ambiguous Expressions
● SynthWorks VHDL type qualifier (type_name') is a mechanism that specifies the type of an operand or return value of a subprogram (or operator).
Z_sv Z_sv <= <= A_sv A_sv + signed'("1010") ; + signed'("1010") ; Effects all numeric Effects all numeric operators in operators in std_logic_arith std_logic_arith ● Leaving out the ' is an error:
 Z_sv <=  Z_sv <= A_sv A_sv + signed("1010") ; + signed("1010") ; ● Without ', it is type casting. Use type casting for:
Z_sv Z_sv <= <= A_sv A_sv + signed(B_slv) ; + signed(B_slv) ; ● Recommended solution, use integer:
Z_sv Z_sv <= <= A_sv A_sv 6; 6; Lewis Copyright © 2003 SynthWorks Design Inc. All Rights Reserved. MAPLD 2003 P19 Addition Operators
Addition Operators:
● SynthWorks +  Arrays with Arrays:
Add_uv Add_uv Sub_uv Sub_uv <= A_uv + B_uv ; <= A_uv + B_uv ; <= C_uv  D_uv ; <= C_uv  D_uv ; • Size of result = • Size of result = • Size of largest array operand • Size of largest array operand • Size of Add = maximum(A, B) • Size of Add = maximum(A, B) • Shorter array gets extended. • Shorter array gets extended. ● Arrays with Integers:
Inc_uv Inc_uv Y_uv Y_uv <= Base_uv + 1 ; <= Base_uv + 1 ; <= A_uv + 45 ; <= A_uv + 45 ; • Caution:: Integers must fit into an • Caution Integers must fit into an array the same size as the result. array the same size as the result. • Extra MSB digits are lost • Extra MSB digits are lost • A must be at least 6 bits • A must be at least 6 bits By convention the left most bit is the MSB
Lewis
Copyright © 2003 SynthWorks Design Inc. All Rights Reserved. MAPLD 2003 P20 Use Integers with Care
● SynthWorks Synthesis tools create a 32bit wide resources for unconstrained integers
signal Y_int, A_int, B_int : integer ; signal Y_int, A_int, B_int : integer ; ... ... Y_int <= A_int + B_int ; Y_int <= A_int + B_int ;
● Do not use unconstrained integers for synthesis ● Specify a range with integers:
signal A_int, B_int: integer range 8 to 7; signal A_int, B_int: integer range 8 to 7; signal Y_int : integer range 16 to 15 ; signal Y_int : integer range 16 to 15 ; ... ... Y_int <= A_int + B_int ; Y_int <= A_int + B_int ; ● Recommendation: Use integers only as constants or literals
Y_uv <= A_uv + 17 ; Y_uv <= A_uv + 17 ; Lewis Copyright © 2003 SynthWorks Design Inc. All Rights Reserved. MAPLD 2003 P21 Comparison Operators
Comparison Operators:
● ● SynthWorks = /= > >= < <= Comparison operators return type boolean Std_Logic is our basic type for design. ● How do we convert from boolean to std_logic? Arrays with Arrays:
AGeB AGeB <= '1' when (A_uv >= B_uv) else '0'; <= '1' when (A_uv >= B_uv) else '0'; AEq15 <= '1' when (A_uv = "1111" ) else '0'; AEq15 <= '1' when (A_uv = "1111" ) else '0'; ● ● Arrays with Integers (special part of arithmetic packages):
DEq15 <= '1' when (D_uv = 15 ) else '0'; DEq15 <= '1' when (D_uv = 15 ) else '0'; Result = Boolean Result = Boolean Input arrays are extended to be the same length Input arrays are extended to be the same length Lewis Copyright © 2003 SynthWorks Design Inc. All Rights Reserved. MAPLD 2003 P22 Multiplication and Division
Multiplication Operators:
● SynthWorks * / mod rem Array Multiplication
signal A_uv, B_uv : unsigned( 7 downto 0) ; signal A_uv, B_uv : unsigned( 7 downto 0) ; signal Z_uv : unsigned(15 downto 0) ; signal Z_uv : unsigned(15 downto 0) ; ... ... Z_uv <= A_uv * B_uv; Z_uv <= A_uv * B_uv; • Size of result = • Size of result = • Sum of the two input arrays • Sum of the two input arrays ● Array with Integer (only numeric_std)
Z_uv <= A_uv * 2 ; Z_uv <= A_uv * 2 ; • Size of result = • Size of result = • 2 * size of array input • 2 * size of array input Note: "// mod rem" not well supported by synthesis tools. Note: " mod rem" not well supported by synthesis tools. Lewis Copyright © 2003 SynthWorks Design Inc. All Rights Reserved. MAPLD 2003 P23 Adder with Carry Out
Unsigned Algorithm:
'0', A(3:0) '0', A(3:0) + '0', B(3:0) + '0', B(3:0) CarryOut, Result(3:0) CarryOut, Result(3:0) SynthWorks
Unsigned Code:
Y5 <= Y5 <= ('0' & A) + ('0' & B); ('0' & A) + ('0' & B); Y <= Y5(3 downto 0) ; Y <= Y5(3 downto 0) ; Co <= Y5(4) ; Co <= Y5(4) ; signal signal signal signal signal signal A, B, Y : unsigned(3 downto 0); A, B, Y : unsigned(3 downto 0); Y5 : unsigned(4 downto 0) ; Y5 : unsigned(4 downto 0) ; Co : std_logic ; Co : std_logic ; Lewis Copyright © 2003 SynthWorks Design Inc. All Rights Reserved. MAPLD 2003 P24 Adder with Carry In
Desired Result:
A(3:0) + B(3:0) + CarryIn A(3:0) + B(3:0) + CarryIn SynthWorks
signal A, B, Y : unsigned(3 downto 0); signal A, B, Y : unsigned(3 downto 0); signal Y5 : unsigned(4 downto 0) ; signal Y5 : unsigned(4 downto 0) ; signal CarryIn : std_logic ; signal CarryIn : std_logic ; Algorithm
A(3:0), '1' A(3:0), '1' + B(3:0), CarryIn + B(3:0), CarryIn Result(4:1), Unused Result(4:1), Unused Example: Carry = 0
0010, 1 0010, 1 0001, 0 0001, 0 0011, 1 0011, 1 Result Result Carry = 1
0010, 1 0010, 1 0001, 1 0001, 1 0100, 0 0100, 0 Code:
Y5 Y5 Y Y
Lewis <= (A & '1') + (B & CarryIn); <= (A & '1') + (B & CarryIn); <= Y5(4 downto 1) ; <= Y5(4 downto 1) ;
Copyright © 2003 SynthWorks Design Inc. All Rights Reserved. MAPLD 2003 P25 ALU Functions
● SynthWorks
● ALU1: OpSel 00 01 10 11 Function A+B C+D E+F G+H Three implementations
● ● ● Tool Driven Resource Sharing Code Driven Resource Sharing Defeating Resource Sharing ● Since OpSel can select only one addition at a time, the operators are mutually exclusive. Lewis Copyright © 2003 SynthWorks Design Inc. All Rights Reserved. MAPLD 2003 P26 Possible Solutions to ALU 1
As Specified:
A B C D E F G H OpSel i0 i1 O i2 i3 sel SynthWorks Optimal results:
A C E G Z OpSel B D F H OpSel
i0 i1 i2 o i3 sel i0 i1 i2 o i3 sel Z ● This transformation of operators is called Resource Sharing Lewis Copyright © 2003 SynthWorks Design Inc. All Rights Reserved. MAPLD 2003 P27 ALU 1: Tool Driven
ToolDrvnProc : process (OpSel,A,B,C,D,E,F,G,H) ToolDrvnProc : process (OpSel,A,B,C,D,E,F,G,H) begin begin case OpSel is case OpSel is when "00" => Z <= A + B ; when "00" => Z <= A + B ; when "01" => Z <= C + D ; when "01" => Z <= C + D ; when "10" => Z <= E + F ; when "10" => Z <= E + F ; when "11" => Z <= G + H ; when "11" => Z <= G + H ; when others => Z <= (others => 'X') ; when others => Z <= (others => 'X') ; end case ; end case ; end process ;  ToolDrvnProc end process ;  ToolDrvnProc SynthWorks ● Important: to ensure resource sharing, operators must be coded in the same process, and same code (case or if) structure. Any potential issues with this? ● Lewis Copyright © 2003 SynthWorks Design Inc. All Rights Reserved. MAPLD 2003 P28 ALU 1: Code Driven
X <= Mux4(OpSel, A, C, E, G) ; X <= Mux4(OpSel, A, C, E, G) ; Y <= Mux4(OpSel, B, D, F, H) ; Y <= Mux4(OpSel, B, D, F, H) ; Z <= X + Y ; Z <= X + Y ; SynthWorks ● Best Synthesis, use for: ● Sharing arithmetic operators ● Sharing comparison operators ● Sharing complex function calls ● Resource sharing often is not possible when using third party arithmetic logic. Lewis Copyright © 2003 SynthWorks Design Inc. All Rights Reserved. MAPLD 2003 P29 ALU 1: Defeating Resource Sharing *
● SynthWorks Bad Code will defeat Resource Sharing.
BadAluProc: BadAluProc: begin begin if (OpSel if (OpSel if (OpSel if (OpSel if (OpSel if (OpSel if (OpSel if (OpSel end process end process process (OpSel, A, B, C, D, E, F, G, H) process (OpSel, A, B, C, D, E, F, G, H) = = = = = = = = ; ; "00") "00") "01") "01") "10") "10") "11") "11") then then then then then then then then Z Z Z Z Z Z Z Z <= <= <= <= <= <= <= <= A A C C E E G G + + + + + + + + B; B; D; D; F; F; H; H; end end end end end end end end if; if; if; if; if; if; if; if; Uses "end if", rather than "elsif" Uses "end if", rather than "elsif" ● * Not Recommended, synthesis tool may create a separate resource for each adder.
Copyright © 2003 SynthWorks Design Inc. All Rights Reserved. Lewis MAPLD 2003 P30 Defeating Resource Sharing
● SynthWorks When does this happen?
case StateReg is case StateReg is when S1 => when S1 => if (in1 = '1') then if (in1 = '1') then Z <= A + B ; Z <= A + B ; ... ... end if ; end if ; when S2 => when S2 => if (in2 = '1') then if (in2 = '1') then Z <= C + D ; Z <= C + D ; ... ... end if ; end if ; ... ... when Sn => when Sn => ... ... when others => when others => ● Separate statemachines and resources
Statemach : process(...) Statemach : process(...) begin begin  generate function  generate function  select logic (OpSel)  select logic (OpSel) end process ; end process ; Resources : process(...) Resources : process(...) begin begin  code:  code:  arithmetic operators  arithmetic operators  comparison operators  comparison operators end process ; end process ; Lewis Copyright © 2003 SynthWorks Design Inc. All Rights Reserved. MAPLD 2003 P31 More Information SynthWorks There is work in progress to extend VHDL's math capability. For more information see the following IEEE working groups websites: Group IEEE 1164 IEEE 1076.3/numeric std IEEE 1076.3/floating point Website http://www.eda.org/vhdlstdlogic http://www.eda.org/vhdlsynth http://www.eda.org/fphdl Also see the DVCon 2003 paper, "Enhancements to VHDL's Packages" which is available at: http://www.synthworks.com/papers Lewis Copyright © 2003 SynthWorks Design Inc. All Rights Reserved. MAPLD 2003 P32 Author Biography SynthWorks Jim Lewis, Director of Training, SynthWorks Design Inc. Jim Lewis, the founder of SynthWorks, has seventeen years of design, teaching, and problem solving experience. In addition to working as a Principal Trainer for SynthWorks, Mr. Lewis does ASIC and FPGA design, custom model development, and consulting. Mr. Lewis is an active member of IEEE Standards groups including, VHDL (IEEE 1076), RTL Synthesis (IEEE 1076.6), Std_Logic (IEEE 1164), and Numeric_Std (IEEE 1076.3). Mr. Lewis can be reached at [email protected], (503) 5904787, or http://www.SynthWorks.com Lewis Copyright © 2003 SynthWorks Design Inc. All Rights Reserved. MAPLD 2003 P33 SynthWorks VHDL Training SynthWorks Comprehensive VHDL Introduction 4 Days http://www.synthworks.com/comprehensive_vhdl_introduction.htm A design and verification engineers introduction to VHDL syntax, RTL coding, and testbenches. Our designer focus ensures that your engineers will be productive in a VHDL design environment. VHDL Coding Styles for Synthesis 4 Days http://www.synthworks.com/vhdl_rtl_synthesis.htm Engineers learn RTL (hardware) coding styles that produce better, faster, and smaller logic. VHDL Testbenches and Verification 3 days http://www.synthworks.com/vhdl_testbench_verification.htm Engineers learn how create a transactionbased verification environment based on bus functional models. For additional courses see:
Lewis http://www.synthworks.com
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