Lab3 - Electrical, Computer, & Telecommunications...

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Unformatted text preview: Electrical, Computer, & Telecommunications Engineering Technology MicroComputers Spring 20073 0618-303 Lab # 3: Software Delays Educational Objective: The educational objective of this laboratory is to develop AVR assemble language programs that implement precise timing delays. Pre-Laboratory: 1. The attached assemble language program Lab3_1 is designed to produce a square wave at PortB, pin B0. Calculate the EXACT frequency and duty cycle of this waveform. The clock cycle period for our mega128.2 board is 0.0625μSec (Frequency = 16 MHz). Be sure to use the 0.0625μSec for all your calculations. To change the default setting on the AVR simulator; select Debug AVR Simulator Option and change the Frequency field to 16 MHz. 2. Enter, assemble, and simulate the program Lab3_1 to verify its operation and confirm your calculations for frequency and duty cycle. 3. Using the knowledge gained from the program Lab3_1; write, assemble, and simulate two assembly language program that meets the following specifications : o The programs will produce a square wave at PortB, pin B0. o The first program will produce a square wave with a frequency of 500 Hz with a duty cycle of 40%. o The second program will produce a square wave with have a frequency of 500 Hz with a duty cycle of 70%. 4. Your prelab is due in the dropbox on MyCourses 1 hour before you lab section. The pre-lab should contains your fully commented code for all three programs and documentation showing your work for the frequency & duty cycle calculations (by hand or excel). Procedure: Fixed Frequency & Duty Cycle 1. Using the AVR Studio 4 tool; build the Lab3_1 program that you wrote and tested in the prelab. 2. Program the mega128.2 Board with the hex file generated in step #1. 3. Using the attached diagram as a guide, connect the oscilloscope to PortB, pin Bo and verify that the program is working. If any changes are necessary, repeat step 1 – 3 until the program is working properly. Selectable Frequency & Duty Cycle 1. Using the AVR Studio 4 tool; build the 40% duty cycle program that you wrote and tested in the pre-lab. 2. Program the mega128.2 Board with the hex file generated in step #1. 3. Using the attached diagram as a guide, connect the oscilloscope to PortB, pin Bo and verify that the program is working. If any changes are necessary, repeat step 1 – 3 until the program is working properly. 4. Repeat steps 1-3 for the 70% duty cycle program. Lab #3 Electrical, Computer, & Telecommunications Engineering Technology MicroComputers Spring 20073 0618-303 Documentation: Using the Lab Report Guidelines for Micro-Computers as a guide, write and submit a report for the work completed in this laboratory. Be sure to discussion the results relative to its educational objective and all observations made. Port B 9 7 5 3 1 10 8 6 Port B 4 2 J18 Scope Probe Ground Lead Lab #3 Electrical, Computer, & Telecommunications Engineering Technology MicroComputers Spring 20073 0618-303 ;*************************************************************************** ;*** *** ;*** Name : Lab3_1 *** ;*** *** ;*** Description : Place your comments here *** ;*** *** ;*************************************************************************** .include "m128def.inc" ; Include.... .def .def .def .def Temp Sig d1 d2 = R16 = R17 = R18 = R19 .cseg .org 0x0000 rjmp START ; Variables.... ; ; ; ; Initialize.... ; ; START: ldi Temp, 0b00000001; Initialize PORT-B.... out DDRB, Temp HIGH: ldi Sig, 0x01 out PORTB, Sig ldi d1, 0xFF HIGH1: ldi d2, 0x16 HIGH2: dec d2 brne HIGH2 dec d1 brne HIGH1 ; HIGH Time... ; ; ; ; ; ; ; ; ; LOW: ldi Sig, 0x00 out PORTB, Sig ldi d1, 0x18 LOW1: ldi d2, 0xC7 LOW2: dec d2 brne LOW2 dec d1 brne LOW1 rjmp HIGH ; LOW Time... ; ; ; ; ; ; ; ; ; ; Repeat.... ;************************************************************************** Lab #3 Electrical, Computer, & Telecommunications Engineering Technology MicroComputers Spring 20073 0618-303 Lab # 3: Software Delays Lab Sign-Offs Name: ______________________ Fixed Frequency & Duty Cycle _______________________________________ _________________ Signature Date 40% Duty Cycle _______________________________________ _________________ Signature Date 70% Duty Cycle _______________________________________ _________________ Signature Date Lab #3 ...
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This note was uploaded on 01/10/2012 for the course ENG 0618-303 taught by Professor Christman during the Spring '07 term at RIT.

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