HW7 - b. Modify this circuit to use D flip-flops c. Why is...

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Electrical, Computer, & Telecommunications Engineering Technology Digital Fundamentals 20072 0618-301 HW #7 HW #7 Due 2/12/08 1. Read Chapter 7 sections 3-8, 9.2, 10 2. Problem 7.5 3. Design a MOD-25 synchronous counter 4. Determine the Q waveform for the FF below. Assume that Q=0 initially. 5. Apply the waveforms above to a D flip flop that triggers on falling clock edges and has active- low PRE and CLR. Assume that D is kept low and that Q is initially high. Draw the Q waveform. 6. In the circuit below, inputs A, B and C are all initially low. Output Y is supposed to go high only when A, B and C go high in a certain sequence. a. Determine the sequence that will make Y go high
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Unformatted text preview: b. Modify this circuit to use D flip-flops c. Why is the start pulse needed? Electrical, Computer, & Telecommunications Engineering Technology Digital Fundamentals 20072 0618-301 HW #7 7. a. How many ffs are required to build a binary counter that counts from 0 to 1023? b. Determine the frequency at the output of the last ff of this counter for an input clock frequency of 2 MHz c. What is the counter’s MOD number? 8. Determine the Q output for a positive-edge triggered D- ff when the waveforms below are applied to it. Assume that Q starts low and the ff has t PHL = 5ns and t PLH = 10ns. Use graph paper for accuracy. The CLK signal frequency is 20MHz CLK 1 0 D 1 0...
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This note was uploaded on 01/10/2012 for the course ENG 0618-301 taught by Professor Christman during the Spring '07 term at RIT.

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HW7 - b. Modify this circuit to use D flip-flops c. Why is...

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