This preview shows pages 1–2. Sign up to view the full content.
This preview has intentionally blurred sections. Sign up to view the full version.View Full Document
Unformatted text preview: b. Modify this circuit to use D flip-flops c. Why is the start pulse needed? Electrical, Computer, & Telecommunications Engineering Technology Digital Fundamentals 20072 0618-301 HW #7 7. a. How many ffs are required to build a binary counter that counts from 0 to 1023? b. Determine the frequency at the output of the last ff of this counter for an input clock frequency of 2 MHz c. What is the counter’s MOD number? 8. Determine the Q output for a positive-edge triggered D- ff when the waveforms below are applied to it. Assume that Q starts low and the ff has t PHL = 5ns and t PLH = 10ns. Use graph paper for accuracy. The CLK signal frequency is 20MHz CLK 1 0 D 1 0...
View Full Document
This note was uploaded on 01/10/2012 for the course ENG 0618-301 taught by Professor Christman during the Spring '07 term at RIT.
- Spring '07