HW6-word - both negative and the sign bit of the result is...

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Digital Fundamentals 20072 0618-301 HW #6 Due 1/31/08 1. Read Chapter 5 Section 2 in the textbook (really read it this time) 2. Problem 5.7 3. In computers and calculators, there are usually circuits that are used to detect an overflow condition. There are several ways to do this. One method that can be used for the adder that operates in the 2’s complement system works as follows: a. Examine the sign bits of the two numbers being added b. Examine the sign bit of the result c. Overflow occurs whenever the numbers being added are both positive and the sign bit of the result is 1 or when the numbers are
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Unformatted text preview: both negative and the sign bit of the result is 0. Design an overflow detection circuit for an adder that adds two n-bit numbers, A and B, to produce an n-bit sum S. A n-1 , B n-1 and S n-1 are the sign bits of A, B and Sum. Use a truth table to get started and remember that overflow cannot occur if the signs of A and B are different. 4. Read Chapter 7 sections 3-6 5. Problem 7.1 6. Apply the waveforms of problem 7.1 to the T flip-flop of figure 7.16(a). Use the D signal from the waveform for the T input to the flip flop. 7. Apply the waveform below to a. A positive-edge triggered J-K flip flop b. A negative-edge triggered J-K flip flop HW #6...
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This note was uploaded on 01/10/2012 for the course ENG 0618-301 taught by Professor Christman during the Spring '07 term at RIT.

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