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Unformatted text preview: both negative and the sign bit of the result is 0. Design an overflow detection circuit for an adder that adds two nbit numbers, A and B, to produce an nbit sum S. A n1 , B n1 and S n1 are the sign bits of A, B and Sum. Use a truth table to get started and remember that overflow cannot occur if the signs of A and B are different. 4. Read Chapter 7 sections 36 5. Problem 7.1 6. Apply the waveforms of problem 7.1 to the T flipflop of figure 7.16(a). Use the D signal from the waveform for the T input to the flip flop. 7. Apply the waveform below to a. A positiveedge triggered JK flip flop b. A negativeedge triggered JK flip flop HW #6...
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This note was uploaded on 01/10/2012 for the course ENG 0618301 taught by Professor Christman during the Spring '07 term at RIT.
 Spring '07
 Christman
 Telecommunications

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