lab3 - Electrical Computer Telecommunications Engineering...

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Electrical, Computer, & Telecommunications Engineering Technology Digital Fundamentals 20072 0618-301 Lab #3 Introduction to CPLD and Xilinx Software Educational Objective: The purpose of this lab is to introduce the use of the Xilinx Software tools to create a design to be programmed in the CPLD (complex programmable logic device) on the d_logic.1 board. Pre-Laboratory: 1. Read sections 2.9 in the textbook 2. Review the d_logic.1 board System Overview found on MyCourses. Procedure: 1. You will use the XILINX tools to create a schematic The schematic will contain all three of the circuits that you designed for lab #2. The inputs A, B and C will be common to all three circuits. Each circuit will have its own output. 2. Listed below are the steps for starting a new project and drawing a schematic Invoke the tool Xilinx ISE from the desktop Go to the ‘File’ pull-down and click on ‘new project’ Enter a project name and location on your S: drive. The choice for Top-Level Module Type should be ‘schematic’. Click ‘next’ Enter the following: o Product Category = All o Device Family = XC9500XL CPLDs o Device = XC9572XL o Package = VQ44 o Speed Grade = -10 o Top-Level Source Type = schematic o Synthesis Tool = XST o Simulator = Modelsim-SE VHDL o Preferred Language = VHDL Click ‘next’ Choose ‘New Source’ Enter a filename and highlight ‘schematic’ in the list on the left Click ‘next’ then ‘finish’ Click ‘next’ on the ‘create new source’ window and ‘next’ on the following window
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This note was uploaded on 01/10/2012 for the course ENG 0618-301 taught by Professor Christman during the Spring '07 term at RIT.

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lab3 - Electrical Computer Telecommunications Engineering...

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