exam1-fall2010 - Name:_ I. (5 0 p o in ts ) M u ltip le c h...

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Name:_______________________________ Page 2 of 12 I. (50 points) Multiple choice/short response Questions (20+30) a. Provide one technique each to address the following types of pipeline hazards (1) WAW __________________________________ (2) WAR ___________________________________ (3) RAW ___________________________________ b. Which of the following is not correct ? (1) The common practice is to use unified caches in L1 for efficient space sharing between instructions and data. (2) The key motivation for having the store queue (or the load/store queue) is to provide precise interrupts. (3) Scoreboard does not use register renaming. (4) Tomasulo’s algorithm uses register renaming. c. Which of the following compiler “optimizations” helps improve IPC? (1) Moving all the uses of a value as immediately after the value is defined (created) as possible. (2) Increasing the distance between the “use” and “define” of a value (3) Minimizing the number of registers used. (4) Unrolling loops. (5) More than one of the above. d. Classify the following statements as TRUE or FALSE. (1) “MIPS” is a poor metric of CPU performance because it omits CPI from among the three components of performance. (2) The key motivation for RISC ISA is code-density. (3) If the instructions of N-different programs can execute (with perfect interleaving) on a single 1-wide in-order pipelined processor with N stages, then the processor offers an instruction throughput improvement of N. (4) BTBs are extremely accurate at identifying return addresses when they
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This note was uploaded on 01/10/2012 for the course ECE 565 taught by Professor Pai during the Fall '11 term at Purdue University-West Lafayette.

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exam1-fall2010 - Name:_ I. (5 0 p o in ts ) M u ltip le c h...

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