Lecture 3 - Pipelines

# Lecture 3 - Pipelines - ECE565 Computer Architecture...

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ECE565: Computer Architecture Instructor: Vijay S. Pai Lecture TA: None Fall 2011 Course administration: via Blackboard ECE 565, Fal 2011 (2) Acknowledgements and Disclaimer •Slides developed by Amir Roth of University of Pennsylvania with sources that included University of Wisconsin slides by Mark Hill, Guri Sohi, Jim Smith, and David Wood. •Slides enhanced by Milo Martin, Mark Hill, and David Wood with sources that included Profs. Asanovic, Falsafi, Hoe, Lipasti, Shen, Smith, Sohi, Thottethodi, Vijaykumar, and Wood Outline • Paper discussion • MIPS ISA examples • Hardware (Pipelining) ECE 565, Fal 2011 3

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Paper – von Neumann Machine • Computer Architecture curriculum • Before computers existed! • Section 1/2 • Stored program computer, memory size driven by applications • Section 3 – CPU/ISA • PC, conditional/unconditional branches • Section 4 – Memory hierarchy + I/O • Hierarchy (capacity/access time), Secondary storage as I/O • Section 5 – Computer Arithmetic • Binary vs. decimal, floating point, multiplier vs divider, accumulator, ripple-carry adder ECE 565, Fal 2011 4 MIPS ISA • Self-study assignment • Two brief exercises to refresh memory • High-level language to MIPS assembly ECE 565, Fal 2011 5 ECE437, Spring 2010 Branches and Jumps While ( i != j) { j= j + i; i= i + 1; } • HLL-> Assembly, \$8 is i, \$9 is j Loop: beq \$8, \$9, Exit // note that the condition is reversed add \$9, \$9, \$8 addi \$8, \$8 , 1 j Loop Exit:
ECE437, Spring 2010 Assembly Exercise for(i=0;i<n;i++) { blah blah } Init: mov \$8,0 Test: slt \$5,\$8,\$9 beq \$5,\$0,Exit Loop: blahblah blahblah Ind: addi \$8,\$8,1 b Test Exit: ECE 565, Fal 2011 8 Next few lectures: Pipelining • Basic Pipelining • Single, in-order issue • Clock rate vs. IPC • Data Hazards • Hardware: stalling and bypassing • Software: pipeline scheduling • Control Hazards • Branch prediction • Precise state Application OS Firmware Compiler CPU I/O Memory Digital Circuits Gates & Transistors ECE 565, Fal 2011 9 Quick Review • Basic datapath : fetch, decode, execute Single-cycle control : hardwired + Low CPI (1) – Long clock period (to accommodate slowest instruction) Multi-cycle control : micro-programmed + Short clock period – High CPI • Can we have both low CPI and short clock period? • Not if datapath executes only one instruction at a time • No good way to make a single instruction go faster insn0.fetch, dec, exec Single-cycle Multi-cycle insn1.fetch, dec, exec insn0.dec insn0.fetch insn1.dec insn1.fetch insn0.exec insn1.exec

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ECE 565, Fal 2011 10 Pipelining • Important performance technique Improves instruction throughput rather instruction latency • Begin with multi-cycle design • When instruction advances from stage 1 to 2 • Allow next instruction to enter stage 1 • Form of parallelism: “insn-stage parallelism” • Individual instruction takes the same number of stages + But instructions enter and leave at a much faster rate • Automotive assembly line analogy insn0.dec insn0.fetch insn1.dec insn1.fetch Multi-cycle Pipelined insn0.exec insn1.exec insn0.dec insn0.fetch insn1.dec insn1.fetch insn0.exec insn1.exec
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Lecture 3 - Pipelines - ECE565 Computer Architecture...

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