Lecture 5 - Out Of Order Issue

Lecture 5 - Out Of Order Issue - The Problem With In-Order...

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ECE 565, Fal 2011 2 The Problem With In-Order Pipelines 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 addf f0,f1, f2 F D E+ E+ E+ W mulf f2 ,f3,f2 F D d* d* E* E* E* E* E* W subf f0,f1,f4 F p* p* D E+ E+ E+ W • What’s happening in cycle 4? mulf stalls due to RAW hazard • OK, this is a fundamental problem subf stalls due to pipeline hazard • Why? subf can’t proceed into D because mulf is there • That is the only reason, and it isn’t a fundamental one • Why can’t subf go into D in cycle 4 and E+ in cycle 6? ECE 565, Fal 2011 3 regfile D$ I$ B P insn buffer S D add p2,p3,p4 sub p2,p4,p5 mul p2,p5,p6 div p4,4,p7 Ready Table P2 P3 P4 P5 P6 P7 Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes div p4,4, p7 mul p2,p5, p6 sub p2,p4, p5 add p2,p3, p4 and Dynamic Scheduling: The Big Picture • Instructions fetch/decoded/renamed into Instruction Buffer • Also called “instruction window” or “instruction scheduler” • Instructions (conceptually) check ready bits every cycle • Execute when ready Time ECE 565, Fal 2011 4 Register Renaming • To eliminate WAW and WAR hazards • Example • Names: r1,r2,r3 • Locations: p1,p2,p3,p4,p5,p6,p7 • Original mapping: r1 p1 , r2 p2 , r3 p3 , p4 p7 are “free” • Renaming +Removes WAW and WAR dependences +Leaves RAW intact! MapTable FreeList Raw insns Renamed insns r1 r2 r3 p1 p2 p3 p4,p5,p6,p7 add r2,r3,r1 add p2,p3,p4 p4 p2 p3 p5,p6,p7 sub r2,r1,r3 sub p2,p4,p5 p4 p2 p5 p6,p7 mul r2,r3,r3 mul p2,p5,p6 p4 p2 p6 p7 div r1,4,r1 div p4,4,p7
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ECE 565, Fal 2011 5 Dynamic Scheduling - OoO Execution • Dynamic scheduling • Totally in the hardware • Also called “out-of-order execution” (OoO) • Fetch many instructions into instruction window • Use branch prediction to speculate past (multiple) branches • Flush pipeline on branch misprediction • Rename to avoid false dependencies (WAW and WAR) • Execute instructions as soon as possible • Register dependencies are known • Handling memory dependencies more tricky (much more later) • Commit instructions in order • Any strange happens before commit, just flush the pipeline • Current machines: 64-100+ instruction scheduling window ECE 565, Fal 2011 6 Static Instruction Scheduling Issue : time at which insns execute Schedule : order in which insns execute • Related to issue, but the distinction is important Scheduling : re-arranging insns to enable rapid issue • Static: by compiler • Requires knowledge of pipeline and program dependences Pipeline scheduling : the basics • Requires large scheduling scope full of independent insns Loop unrolling , software pipelining: increase scope for loops Trace scheduling : increase scope for non-loops Anything software can do hardware can do better ECE 565, Fal 2011 7 Motivation Dynamic Scheduling Dynamic scheduling (out-of-order execution) • Execute insns in non-sequential (non-VonNeumann) order… +Reduce RAW stalls +Increase pipeline and functional unit (FU) utilization • Original motivation was to increase FP unit utilization
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Lecture 5 - Out Of Order Issue - The Problem With In-Order...

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