Lecture 6 - Precise State

Lecture 6 Precise - ECE565 Computer Architecture Instructor Vijay S Pai Fall 2011 ECE 565 Fall 2011 1 This Unit Dynamic Scheduling II Application

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ECE565: Computer Architecture Instructor: Vijay S. Pai Fall 2011 1 ECE 565, Fal 2011 ECE 565, Fal 2011 2 This Unit: Dynamic Scheduling II • Previously: dynamic scheduling • Insn buffer + scheduling algorithms • Scoreboard: no register renaming • Tomasulo: register renaming • Now: add speculation, precise state • Re-order buffer • PentiumPro vs. MIPS R10000 • Also: dynamic load scheduling • Out-of-order memory operations Application OS Firmware Compiler CPU I/O Memory Digital Circuits Gates & Transistors ECE 565, Fal 2011 3 Superscalar + Out-of-Order + Speculation • Three great tastes that taste great together • CPI 1? • Go superscalar • Superscalar increases RAW hazards? • Go out-of-order (OoO) • RAW hazards still a problem? • Build a larger window • Branches a problem for filling large window? • Add control speculation
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ECE 565, Fal 2011 4 Speculation and Precise Interrupts • Why are we discussing these together? • Sequential (vN) semantics for interrupts • All insns before interrupt should be complete • All insns after interrupt should look as if never started (abort) Basically want same thing for mis-predicted branch • What makes precise interrupts difficult? • OoO completion must undo post-interrupt writebacks • Same thing for branches • In-order branches complete before younger insns writeback • OoO not necessarily Precise interrupts, mis-speculation recovery: same problem Same problem same solution ECE 565, Fal 2011 5 Precise State Speculative execution requires (Ability to) abort & restart at every branch Abort & restart at every load useful for load speculation (later) And for shared memory multiprocessing (much later) Precise synchronous (program-internal) interrupts require Abort & restart at every load, store, ?? Precise asynchronous (external) interrupts require Abort & restart at every ?? Bite the bullet Implement abort & restart at every insn Called “precise state” ECE 565, Fal 2011 6 Precise State Options • Imprecise state: ignore the problem! – Makes page faults (any restartable exceptions) difficult – Makes speculative execution almost impossible • IEEE standard strongly suggests precise state • Compromise: Alpha implemented precise state only for integer ops • Force in-order completion (W): stall pipe if necessary – Slow • Precise state in software: trap to recovery routine – Implementation dependent • Trap on every mis-predicted branch (you must be joking) • Precise state in hardware + Everything is better in hardware (except policy)
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ECE 565, Fal 2011 7 The Problem with Precise State Problem: writeback combines two separate functions • Forwards values to younger insns: OK for this to be out-of-order • Write values to registers: would like this to be in-order • Similar problem (decode) for OoO execution: solution?
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This note was uploaded on 01/10/2012 for the course ECE 565 taught by Professor Pai during the Fall '11 term at Purdue University-West Lafayette.

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Lecture 6 Precise - ECE565 Computer Architecture Instructor Vijay S Pai Fall 2011 ECE 565 Fall 2011 1 This Unit Dynamic Scheduling II Application

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