Lecture 9 -Memory

Lecture 9 -Memory - ECE565: Computer Architecture...

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ECE565: Computer Architecture Instructor: Vijay Pai Fall 2011 1 ECE 565, Fal 2011 ECE 565, Fal 2011 2 This Unit: Main Memory • Memory hierarchy review • Virtual memory • Address translation and page tables • Virtual memory’s impact on caches • Page-based protection • Organizing a memory system • Bandwidth matching • Error correction Application OS Firmware Compiler I/O Memory Digital Circuits Gates & Transistors CPU ECE 565, Fal 2011 3 Static Random Access Memory - Read Sequence 1. address decode 2. drive row select 3. selected bit-cells drive bitlines 4. diff. sensing and col. select 5. precharge all bitlines - Access latency dominated by steps 2 and 3 - Cycling time dominated by steps 2, 3 and 5 - step 2 proportional to 2 m - step 3 and 5 proportional to 2 n - usually encapsulated by synchronous (sometime pipelined) interface logic bit-cell array 2 n row x 2 m -col (n m to minmize overall latency) sense amp and mux 2 m diff pairs 2 n n m 1 row select bitline _bitline n+m
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ECE 565, Fal 2011 4 Dynamic Random Access Memory - Bits stored as charges on node capacitance (non-restorative) - bit cell loses charge when read - bit cell loses charge over time - Read Sequence 1~3 same as SRAM 4. a “flip-flopping” sense amp amplifies and regenerates the bitline, data bit is mux’ed out 5. precharge all bitlines - A DRAM controller must periodically, either distributed or in a burst, read all rows within the allowed refresh time (10s of ms) synchronous interfaces - various hacks to allow faster repeated reads to the same row row enable _bitline bit-cell array 2 n row x 2 m -col (n m to minmize overall latency) sense amp and mux 2 m 2 n n m 1 RAS CAS A DRAM die comprises of multiple such arrays ECE 565, Fal 2011 5 Brief History of DRAM • DRAM (memory): a major force behind computer industry • Modern DRAM came with introduction of IC (1970) • Preceded by magnetic “core” memory (1950s) • Each cell was a small magnetic “donut” • And by mercury delay lines before that (ENIAC) • Re-circulating vibrations in mercury tubes “the one single development that put computers on their feet was the invention of a reliable form of memory, namely the core memory… It’s cost was reasonable, it was reliable, and because it was reliable it could in due course be made large” Maurice Wilkes Memoirs of a Computer Programmer, 1985 DRAM Basics [Jacob and Wang] • Precharge and Row Access ECE 565, Fal 2011 6
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DRAM Basics, cont. • Column Access ECE 565, Fal 2011 7 DRAM Basics, cont. • Data Transfer ECE 565, Fal 2011 8 Open v. Closed Pages • Open Page • Row stays active until another row needs to be accessed • Acts as memory-level cache to reduce latency • Variable access latency complicates memory controller • Higher power dissipation (sense amps remain active) • Closed Page • Immediately deactivate row after access • All accesses become Activate Row, Read/Write, Precharge • Complex power v. performance trade off ECE 565, Fal 2011 9
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ECE 565, Fal 2011 10 DRAM Bandwidth • Use multiple DRAM chips to increase bandwidth
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Lecture 9 -Memory - ECE565: Computer Architecture...

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