Unformatted text preview: • Section 1
By: Mahdi Hassanpour
Wednesday, January 11, 2012 Mahdi Hassanpour Contents:
Block Diagram and Pin Description of the 8051
Some Simple Instructions
Structure of Assembly language and Running
an 8051 program
Memory mapping in 8051
8051 Flag bits and the PSW register
16-bit, BCD and Signed Arithmetic in 8051
Stack in the 8051
LOOP and JUMP Instructions
I/O Port Programming Wednesday, January 11, 2012 Mahdi Hassanpour Introduction General-purpose microprocessor
• CPU for Computers
No RAM, ROM, I/O on CPU chip itself
Example ： Intel’s x86, Motorola’s 680x0 CPU
Microprocessor Many chips on mother’s board Data Bus RAM ROM I/O
Port Address Bus
General-Purpose Microprocessor System
Wednesday, January 11, 2012 Mahdi Hassanpour Timer Serial
Port Microcontroller :
• A smaller computer
• On-chip RAM, ROM, I/O ports...
• Example ： Motorola’s 6811, Intel’s 8051, Zilog’s Z8 and PIC 16X CPU
Port RAM ROM
Port Wednesday, January 11, 2012 A single chip
Mahdi Hassanpour Microprocessor vs. Microcontroller
• CPU is stand-alone, RAM,
ROM, I/O, timer are separate
• designer can decide on the
amount of ROM, RAM and
• general-purpose Wednesday, January 11, 2012 Microcontroller
• CPU, RAM, ROM, I/O and
timer are all on a single chip
• fix amount of on-chip ROM,
RAM, I/O ports
• for applications in which cost,
power and space are critical
• single-purpose Mahdi Hassanpour Embedded System
• Embedded system means the processor is embedded into that
• An embedded product uses a microprocessor or microcontroller to
do one task only.
• In an embedded system, there is only one application software that
is typically burned into ROM.
• Example ： printer, keyboard, video game player Wednesday, January 11, 2012 Mahdi Hassanpour Three criteria in Choosing a Microcontroller
1. meeting the computing needs of the task efficiently and cost
• speed, the amount of ROM and RAM, the number of I/O ports
and timers, size, packaging, power consumption
• easy to upgrade
• cost per unit
1. availability of software development tools
• assemblers, debuggers, C compilers, emulator, simulator,
1. wide availability and reliable sources of the microcontrollers. Wednesday, January 11, 2012 Mahdi Hassanpour Block Diagram
code Timer/Counter On-chip
RAM Timer 1
Timer 0 CPU OSC Bus
Control 4 I/O Ports P0 P1 P2 P3 Address/Data
Wednesday, January 11, 2012 Mahdi Hassanpour Serial
Port TxD RxD Counter
Inputs Comparison of the 8051 Family Members Feature
ROM (program space in bytes) 4K
6 Wednesday, January 11, 2012 Mahdi Hassanpour 8052
6 Wednesday, January 11, 2012 Mahdi Hassanpour Pin Description of the 8051
Wednesday, January 11, 2012 1
(8031) Mahdi Hassanpour 40
P2.0(A8) Pins of 8051 （ 1/4 （
• Vcc ： pin 40 ：：
– Vcc provides supply voltage to the chip.
– The voltage source is +5V.
• GND ： pin 20 ：： ground
• XTAL1 and XTAL2 ： pins 19,18 ：：
– These 2 pins provide external clock.
– Way 1 ： using a quartz crystal oscillator – Way 2 ： using a TTL oscillator – Example 4-1 shows the relationship between XTAL and the
machine cycle. Wednesday, January 11, 2012 Mahdi Hassanpour Pins of 8051 （ 2/4 （
• RST ： pin 9 ：： reset
– It is an input pin and is active high ： normally low ： .
• The high pulse must be high at least 2 machine cycles.
– It is a power-on reset.
• Upon applying a high pulse to RST, the microcontroller will
reset and all values in registers will be lost.
• Reset values of some 8051 registers – Way 1 ： Power-on reset circuit – Way 2 ： Power-on reset with debounce Wednesday, January 11, 2012 Mahdi Hassanpour Pins of 8051 （ 3/4 （
• /EA ： pin 31 ：： external access
– There is no on-chip ROM in 8031 and 8032 .
– The /EA pin is connected to GND to indicate the code is stored
– /PSEN ： ALE are used for external ROM.
– For 8051, /EA pin is connected to Vcc.
– “/” means active low.
• /PSEN ： pin 29 ：： program store enable
– This is an output pin and is connected to the OE pin of the ROM.
– See Chapter 14. Wednesday, January 11, 2012 Mahdi Hassanpour Pins of 8051 （ 4/4 （
• ALE ： pin 30 ：： address latch enable
– It is an output pin and is active high.
– 8051 port 0 provides both address and data.
– The ALE pin is used for de-multiplexing the address and data by
connecting to the G pin of the 74LS373 latch.
• I/O port pins
– The four ports P0, P1, P2, and P3.
– Each port uses 8 pins.
– All I/O pins are bi-directional. Wednesday, January 11, 2012 Mahdi Hassanpour Figure 4-2 (a). XTAL Connection to 8051
• Using a quartz crystal oscillator
We can observe the frequency on the XTAL2 pin.
GND Wednesday, January 11, 2012 Mahdi Hassanpour Figure 4-2 (b). XTAL Connection to an External Clock Source N
• Using a TTL oscillator
XTAL2 is unconnected. EXTERNAL
SIGNAL XTAL2 XTAL1 GND Wednesday, January 11, 2012 Mahdi Hassanpour Example :
Find the machine cycle for
(a) XTAL = 11.0592 MHz
(b) XTAL = 16 MHz.
(a) 11.0592 MHz / 12 = 921.6 kHz;
machine cycle = 1 / 921.6 kHz = 1.085 µs
(b) 16 MHz / 12 = 1.333 MHz;
machine cycle = 1 / 1.333 MHz = 0.75 µs Wednesday, January 11, 2012 Mahdi Hassanpour RESET Value of Some 8051 Registers: Register
DPTR Reset Value
0000 RAM are all zero.
Wednesday, January 11, 2012 Mahdi Hassanpour Figure 4-3 (a). Power-On RESET Circuit
10 uF 31
30 pF 8.2 K 11.0592 MHz 19
18 30 pF EA/VPP
X2 9 RST Wednesday, January 11, 2012 Mahdi Hassanpour Figure 4-3 (b). Power-On RESET with Debounce
10 uF 30 pF 9 EA/VPP
RST 8.2 K Wednesday, January 11, 2012 Mahdi Hassanpour Pins of I/O Port
• The 8051 has four I/O ports
– Port 0 ： pins 32-39 ：： P0 ： P0.0 ： P0.7 ：
– Port 1 ： pins 1-8 ： ： P1 ： P1.0 ： P1.7 ：
– Port 2 ： pins 21-28 ：： P2 ： P2.0 ： P2.7 ：
– Port 3 ： pins 10-17 ：： P3 ： P3.0 ： P3.7 ：
– Each port has 8 pins.
• Named P0.X ： X=0,1,...,7 ： , P1.X, P2.X, P3.X
• Ex ： P0.0 is the bit 0 ： LSB ： of P0
• Ex ： P0.7 is the bit 7 ： MSB ： of P0
• These 8 bits form a byte.
• Each port can be used as input or output (bi-direction).
Wednesday, January 11, 2012 Mahdi Hassanpour Registers
R0 DPTR DPH DPL R1
R2 PC PC R3
R4 Some 8051 16-bit Register R5
Some 8-bitt Registers of
the 8051 Wednesday, January 11, 2012 Mahdi Hassanpour Some Simple Instructions
DPH,#76H MOV ; dest = source
;A=‘r’ OR 72H
;B=the content of F9’th byte of RAM P1,A ;mov A to port 1 Note 1:
After instruction “MOV ≠
A,72H ” the content of 72’th byte of RAM will replace in Accumulator. 8086
A,#’r’ MOV A,72H MOV A,3 Note 2:
MOV A,R3 ≡ Wednesday, January 11, 2012 Mahdi Hassanpour ADD A, Source ;A=A+SOURCE ADD A,#6 ;A=A+6 ADD A,R6 ;A=A+R6 ADD A,6 ;A=A+ or A=A+R6 ADD A,0F3H ;A=A+[0F3H] Wednesday, January 11, 2012 Mahdi Hassanpour SETB
05 ; bit=1
;bit 0 from port 0 =1
;bit 7 from port 3 =1
;bit 2 from ACCUMULATOR =1
;set high D5 of RAM loc. 20h
Page 359,360 Note: CLR instruction is as same as SETB
But following instruction is only for CLR:
Wednesday, January 11, 2012 Mahdi Hassanpour SUBB A,source ;A=A-source-CY SETB C
SUBB A,R5 ADC
;A=A-R5-1 A,source ;A=A+source+CY
A,R5 Wednesday, January 11, 2012 ;A=A+R5+1 Mahdi Hassanpour DEC
40H ; =-1 CPL A ;1’s complement Example:
SJMP A,#55H ;A=01010101 B
L01 NOP & RET & RETI
All are like 8086 instructions. Wednesday, January 11, 2012 Mahdi Hassanpour CALL ANL - ORL - XRL
RR – RL – RRC – RLC
RR A Wednesday, January 11, 2012 Mahdi Hassanpour A Structure of Assembly language
and Running an 8051 program
Other obj file
Myfile.hex Wednesday, January 11, 2012 Mahdi Hassanpour Memory mapping in 8051
• ROM memory map in 8051 family
0000H 8k 32k
0000H 0000H 0FFFH
AT89C52 7FFFH from Atmel Corporation Wednesday, January 11, 2012 Mahdi Hassanpour from Dallas Semiconductor • RAM memory space allocation in the 8051
Scratch pad RAM 30H
1FH Register Bank 3 18H
17H Register Bank 2 10H
08H Stack) Register Bank 1( 07H Register Bank 0 00H Wednesday, January 11, 2012 Mahdi Hassanpour 8051 Flag bits and the PSW register
• PSW Register
CY AC F0 RS1 RS0 OV Carry flag
Auxiliary carry flag
Available to the user for general purpose
Register Bank selector bit 1
Register Bank selector bit 0
User define bit
Parity flag Set/Reset odd/even parity RS1 RS0 Register Bank -- P PSW.7
-P Address 0 0 0 00H-07H 0 1 1 08H-0FH 1 0 2 10H-17H 1 1 3 18H-1FH Wednesday, January 11, 2012 Mahdi Hassanpour Instructions that Affect Flag Bits: Note: X can be 0 or 1 Wednesday, January 11, 2012 Mahdi Hassanpour Example:
P=1 Wednesday, January 11, 2012 Mahdi Hassanpour 10011100
P=0 Addressing Modes
Indexed Wednesday, January 11, 2012 Mahdi Hassanpour Immediate Addressing Mode
P1,#65H Example :
data1: EQU 30 R0,Num
db Wednesday, January 11, 2012 “IRAN” Mahdi Hassanpour Register Addressing Mode
MOV Rn, A
DPL, R6 MOV
MOV DPTR, A
Rm, Rn Wednesday, January 11, 2012 ;n=0,..,7 Mahdi Hassanpour Direct Addressing Mode
Although the entire of 128 bytes of RAM can be accessed using direct
addressing mode, it is most often used to access RAM loc. 30 – 7FH.
MOV R0, 40H
6, 2 ; ≡ MOV A, R4
; copy R2 to R6
; MOV R6,R2 is invalid ! SFR register and their address
MOV 0E0H, #66H
80H,A Wednesday, January 11, 2012 ; ≡ MOV A,#66H
; ≡ MOV B, R2
; ≡ MOV P1,A
Mahdi Hassanpour Bit Addressable
Page 359,360 Register Indirect Addressing Mode
• In this mode, register is used as a pointer to the data. MOV A,@Ri MOV ; move content of RAM loc.Where address is held by Ri into A
( i=0 or 1 ) @R1,B In other word, the content of register R0 or R1 is sources or target in MOV, ADD and SUBB
Write a program to copy a block of 10 bytes from RAM location sterting at 37h to RAM
location starting at 59h.
L1: MOV A,@R0
Wednesday, January 11, 2012 ; source pointer
; dest pointer
; counter jump Mahdi Hassanpour Indexed Addressing Mode And On-Chip
• This mode is widely used in accessing data elements
of look-up table entries located in the program (code)
space ROM at the 8051
A= content of address A +DPTR from ROM
Because the data elements are stored in the program
(code ) space ROM of the 8051, it uses the instruction
MOVC instead of MOV. The “C” means code.
Wednesday, January 11, 2012 Mahdi Hassanpour • Example:
Assuming that ROM space starting at 250h contains “Hello.”, write a program to transfer the
bytes into RAM locations starting at 40h.
Notice the NULL character ,0, as end of string and how we use the JZ instruction to
Wednesday, January 11, 2012 Mahdi Hassanpour • Example:
Write a program to get the x value from P1 and send x2 to P2, continuously .
MOV DPTR, #TAB1
END Wednesday, January 11, 2012 Mahdi Hassanpour 16-bit, BCD and Signed
Arithmetic in 8051
Exercise: Write a program to add n 16-bit number. Get n
from port 1. And sent Sum to LCD
a) in hex
b) in decimal Write a program to subtract P1 from P0 and send
result to LCD
(Assume that “ACAL DISP” display A to LCD ) Wednesday, January 11, 2012 Mahdi Hassanpour MUL & DIV
AB • MUL
AB Wednesday, January 11, 2012 ;B|A = A*B ;25H*65H=0E99
;A = A/B, B = A mod B ;A=2, B=5
Mahdi Hassanpour Stack in the 8051
• The register used to access
the stack is called SP (stack
pointer) register. 7FH
Scratch pad RAM
30H • The stack pointer in the
8051 is only 8 bits wide,
which means that it can take
value 00 to FFH. When
8051 powered up, the SP
register contains value 07. Wednesday, January 11, 2012 2FH
00H Mahdi Hassanpour Register Bank 3
Register Bank 2
Stack) Register Bank 1(
Register Bank 0 Example:
4 0BH 0BH 0BH 0BH 0AH 0AH 0AH 0AH F3 09H 09H 09H 12 09H 12 08H 08H 08H 25 08H 25 Start SP=07H Wednesday, January 11, 2012 25 SP=08H SP=09H Mahdi Hassanpour SP=08H LOOP and JUMP Instructions DJNZ:
Write a program to clear ACC, then
add 3 to the accumulator ten time
R2,AGAING ;repeat until R2=0 (10 times)
R5,A Wednesday, January 11, 2012 Mahdi Hassanpour • Other conditional jumps :
JZ Jump if A=0 JNZ Jump if A/=0 DJNZ Decrement and jump if A/=0 CJNE A,byte Jump if A/=byte CJNE reg,#data Jump if byte/=#data JC Jump if CY=1 JNC Jump if CY=0 JB Jump if bit=1 JNB Jump if bit=0 JBC Jump if bit=1 and clear bit Wednesday, January 11, 2012 Mahdi Hassanpour SJMP and LJMP:
LJMP is an unconditional jump. It is a 3-byte instruction in
which the first byte is the opcode, and the second and third
bytes represent the 16-bit address of the target location. The
20byte target address allows a jump to any memory location
from 0000 to FFFFH.
In this 2-byte instruction. The first byte is the opcode and the
second byte is the relative address of the target location. The
relative address range of 00-FFH is divided into forward and
backward jumps, that is , within -128 to +127 bytes of
memory relative to the address of the current PC.
Wednesday, January 11, 2012 Mahdi Hassanpour CJNE , JNC
Write a program that compare R0,R1.
If R0>R1 then send 1 to port 2,
else if R0<R1 then send 0FFh to port 2,
else send 0 to port 2. Wednesday, January 11, 2012 Mahdi Hassanpour CALL Instructions
Another control transfer instruction is the CALL
instruction, which is used to call a subroutine.
• LCALL(long call)
In this 3-byte instruction, the first byte is the opcode
an the second and third bytes are used for the address
of target subroutine. Therefore, LCALL can be used
to call subroutines located anywhere within the 64K
byte address space of the 8051.
Wednesday, January 11, 2012 Mahdi Hassanpour • ACALL (absolute call)
ACALL is 2-byte instruction in contrast to LCALL,
which is 13 bytes. Since ACALL is a 2-byte instruction,
the target address of the subroutine must be within 2K
bytes address because only 11 bits of the 2 bytes are used
for the address. There is no difference between ACALL
and LCALL in terms of saving the program counter on
the stack or the function of the RET instruction. The only
difference is that the target address for LCALL can be
anywhere within the 64K byte address space of the 8051
while the target address of ACALL must be within a 2Kbyte range.
Wednesday, January 11, 2012 Mahdi Hassanpour I/O Port Programming
Port 1 ： pins 1-8 ： • Port 1 is denoted by P1.
– P1.0 ~ P1.7
• We use P1 as examples to show the operations on ports.
– P1 as an output port (i.e., write CPU data to the external pin)
– P1 as an input port (i.e., read pin data into CPU bus) Wednesday, January 11, 2012 Mahdi Hassanpour A Pin of Port 1
Read latch TB2 Vcc
Load(L1) Internal CPU
bus D Write to latch Clk P1.X
pin Q P1.X
Q M1 TB1 P0.x Read pin Wednesday, January 11, 2012 Mahdi Hassanpour 8051 IC Hardware Structure of I/O Pin
• Each pin of I/O ports
– Internal CPU bus ： communicate with CPU
– A D latch store the value of this pin
• D latch is controlled by “Write to latch”
– Write to latch ： 1 ： write data into the D latch
– 2 Tri-state buffer ：：
• TB1: controlled by “Read pin”
– Read pin ： 1 ： really read the data present at the pin
• TB2: controlled by “Read latch”
– Read latch ： 1 ： read value from internal latch
– A transistor M1 gate
• Gate=0: open
• Gate=1: close Wednesday, January 11, 2012 Mahdi Hassanpour Tri-state Buffer
Output Input Tri-state control
(active high) L L H Wednesday, January 11, 2012 H H H Mahdi Hassanpour Low Highimpedance
(open-circuit) Writing “1” to Output Pin P1.X
Read latch Vcc TB2 Load(L1) 2. output pin is Vcc 1. write a 1 to the pin
bus D Write to latch Clk 1 Q P1.X
Q 0 M1 TB1
Read pin Wednesday, January 11, 2012 Mahdi Hassanpour 8051 IC output 1 Writing “0” to Output Pin P1.X
Read latch Vcc TB2 Load(L1) 2. output pin is ground 1. write a 0 to the pin
bus D Write to latch Clk 0 Q P1.X
Q 1 M1 TB1
Read pin Wednesday, January 11, 2012 Mahdi Hassanpour 8051 IC output 0 Port 1 as Output ： Write to a Port ：
• Send data to Port 1 ： BACK: MOV
SJMP BACK – Let P1 toggle.
– You can write to P1 directly.
Wednesday, January 11, 2012 Mahdi Hassanpour Reading Input v.s. Port Latch
• When reading ports, there are two possibilities ：
– Read the status of the input pin. ： from external pin value ：
• MOV A, PX
• JNB P2.1, TARGET ; jump if P2.1 is not set
P2.1, TARGET ; jump if P2.1 is set
• Figures C-11, C-12
– Read the internal latch of the output port.
• ANL P1, A
; P1 ← P1 AND A
• ORL P1, A
; P1 ← P1 OR A
• INC P1
; increase P1
• Figure C-17
• Table C-6 Read-Modify-Write Instruction (or Table 8-5)
• See Section 8.3
Wednesday, January 11, 2012 Mahdi Hassanpour Reading “High” at Input Pin
1. TB2 write a 1 to the pin MOV
Internal CPU bus 2. MOV A,P1 Vcc external pin=High
Load(L1) D 1 Q 1 P1.X
Write to latch Clk 0 Q M1 TB1
3. Read pin=1 Read latch=0
Write to latch=1
Wednesday, January 11, 2012 8051 IC
Mahdi Hassanpour P1.X pin Reading “Low” at Input Pin
1. Vcc 2. MOV A,P1 TB2 write a 1 to the pin Load(L1) external pin=Low MOV P1,#0FFH
Internal CPU bus D 1 Q 0 P1.X
Write to latch Clk Q 0 M1 TB1
3. Read pin=1 Read latch=0
Write to latch=1
Wednesday, January 11, 2012 8051 IC
Mahdi Hassanpour P1.X pin Port 1 as Input ： Read from Port ：
• In order to make P1 an input, the port must be programmed by writing 1 to
all the bit. BACK: MOV
;make P1 an input port
;get data from P0
;send data to P2 – To be an input port, P0, P1, P2 and P3 have similar methods. Wednesday, January 11, 2012 Mahdi Hassanpour Instructions For Reading an Input Port
• Following are instructions for reading external pins of ports: Mnemonics Examples Description MOV A,PX MOV A,P2 Bring into A the data at P2
pins JNB PX.Y,.. JNB P2.1,TARGET Jump if pin P2.1 is low JB PX.Y,.. JB P1.3,TARGET Jump if pin P1.3 is high MOV C,PX.Y MOV C,P2.4 Copy status of pin P2.4 to CY Wednesday, January 11, 2012 Mahdi Hassanpour Reading Latch
• Exclusive-or the Port 1 ：
MOV P1,#55H ;P1=01010101
ORL P1,#0F0H ;P1=11110101
1. The read latch activates TB2 and bring the data from the Q latch into
• Read P1.0=0
2. CPU performs an operation.
• This data is ORed with bit 1 of register A. Get 1.
3. The latch is modified.
• D latch of P1.0 has value 1.
4. The result is written to the external pin.
• External pin (pin 1: P1.0) has value 1. Wednesday, January 11, 2012 Mahdi Hassanpour Reading the Latch
1. Read pin=0 Read latch=1 Write to
latch=0 (Assume P1.X=0 initially)
Read latch Vcc
TB2 2. CPU compute P1.X OR 1 Load(L1)
0 Internal CPU bus D
1 Write to latch
3. write result to latch Read
Write to latch=1 0 Q
P1.X Clk 1 0
M1 Q TB1
Wednesday, January 11, 2012 Mahdi Hassanpour 4. P1.X=1
P1.X pin Read-modify-write Feature
• Read-modify-write Instructions
– Table C-6
• This features combines 3 actions in a single instruction ：
1. CPU reads the latch of the port
2. CPU perform the operation
3. Modifying the latch
4. Writing to the pin
– Note that 8 pins of P1 work independently. Wednesday, January 11, 2012 Mahdi Hassanpour Port 1 as Input ： Read from latch ：
• Exclusive-or the Port 1 ：
MOV P1,#55H ;P1=01010101
AGAIN: XOR P1,#0FFH ;complement
– Note that the XOR of 55H and FFH gives AAH.
– XOR of AAH and FFH gives 55H.
– The instruction read the data in the latch (not from the pin).
– The instruction result will put into the latch and the pin. Wednesday, January 11, 2012 Mahdi Hassanpour Read-Modify-Write Instructions
Mnemonics Example ANL ANL P1,A ORL ORL P1,A XRL XRL P1,A JBC PX.Y, TARGET JBC P1.1, TARGET CPL CPL P1.2 INC INC DEC DEC P1 DJNZ PX, TARGET DJNZ P1,TARGET MOV PX.Y,C MOV P1.2,C CLR PX.Y CLR P1.3 SETB PX.Y SETB P1.4 Wednesday, January 11, 2012 Mahdi Hassanpour P1 You are able to answer this Questions:
• How to write the data to a pin ：
• How to read the data from the pin ：
– Read the value present at the external pin.
• Why we need to set the pin first ：
– Read the value come from the latch ： not from the external
pin ： .
• Why the instruction is called read-modify write? Wednesday, January 11, 2012 Mahdi Hassanpour Other Pins
• P1, P2, and P3 have internal pull-up resisters.
– P1, P2, and P3 are not open drain.
• P0 has no internal pull-up resistors and does not connects to
Vcc inside the 8051.
– P0 is open drain.
– Compare the figures of P1.X and P0.X. • However, for a programmer, it is the same to program P0, P1,
P2 and P3.
• All the ports upon RESET are configured as output. Wednesday, January 11, 2012 Mahdi Hassanpour A Pin of Port 0
Read latch TB2 Internal CPU
bus D Write to latch Clk P0.X
pin Q P1.X
Q M1 TB1
Read pin Wednesday, January 11, 2012 Mahdi Hassanpour 8051 IC P1.x Port 0 ： pins 32-39 ：
• P0 is an open drain.
– Open drain is a term used for MOS chips in the same way
that open collector is used for TTL chips. • When P0 is used for simple data I/O we must connect it to
external pull-up resistors.
– Each pin of P0 must be connected externally to a 10K ohm
– With external pull-up resistors connected upon reset, port 0
is configured as an output port. Wednesday, January 11, 2012 Mahdi Hassanpour Port 0 with Pull-Up Resistors
Vcc 10 K Wednesday, January 11, 2012 Port 0 P0.0
P0.7 Mahdi Hassanpour Dual Role of Port 0
• When connecting an 8051/8031 to an external memory, the 8051
uses ports to send addresses and read instructions.
– 8031 is capable of accessing 64K bytes of external memory.
– 16-bit address ： P0 provides both address A0-A7, P2 provides
– Also, P0 provides data lines D0-D7.
• When P0 is used for address/data multiplexing, it is connected to the
74LS373 to latch the address.
– There is no need for external pull-up resistors as shown in
Chapter 14. Wednesday, January 11, 2012 Mahdi Hassanpour 74LS373
P0.0 74LS373 G
D P0.7 OE
P2.0 A8 P2.7 A15 8051 Wednesday, January 11, 2012 Mahdi Hassanpour ROM Reading ROM (1/2) P0.0 2. 74373 latches the
address and send to
A0 P0.7 A7 PSEN
ALE 1. Send address to
ROM D Address
P2.0 A8 P2.7 A12 8051
Wednesday, January 11, 2012 Mahdi Hassanpour ROM Reading ROM (2/2)
P0.7 2. 74373 latches the
address and send to
ROM 74LS373 G
D Address OE
D7 EA 3. ROM send the
P2.0 A8 P2.7 A12 8051 Wednesday, January 11, 2012 Mahdi Hassanpour ROM ALE Pin
• The ALE pin is used for de-multiplexing the
address and data by connecting to the G pin of
the 74LS373 latch.
– When ALE=0, P0 provides data D0-D7.
– When ALE=1, P0 provides address A0-A7.
– The reason is to allow P0 to multiplex address and
data. Wednesday, January 11, 2012 Mahdi Hassanpour Port 2 ： pins 21-28 ：
• Port 2 does not need any pull-up resistors since
it already has pull-up resistors internally.
• In an 8031-based system, P2 are used to
provide address A8-A15. Wednesday, January 11, 2012 Mahdi Hassanpour Port 3 ： pins 10-17 ：
• Port 3 does not need any pull-up resistors since it already
has pull-up resistors internally.
• Although port 3 is configured as an output port upon reset,
this is not the way it is most commonly used.
• Port 3 has the additional function of providing signals.
– Serial communications signal ： RxD, TxD ： Chapter 10 ：
– External interrupt ： /INT0, /INT1 ： Chapter 11 ：
– Timer/counter ： T0, T1 ： Chapter 9 ：
– External memory accesses in 8031-based
system ： /WR, /RD ： Chapter 14 ：
Wednesday, January 11, 2012 Mahdi Hassanpour Port 3 Alternate Functions
P3 Bit Function Pin P3.0
17 Wednesday, January 11, 2012 Mahdi Hassanpour ...
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This note was uploaded on 01/11/2012 for the course ELECTRIC 101 taught by Professor Chen during the Spring '11 term at National Chiao Tung University.
- Spring '11