chap4 - ' $ EE432 Field-E ect Transistors Chapter 4 &...

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Unformatted text preview: ' $ EE432 Field-E ect Transistors Chapter 4 & Patrick Roblin T.H.E OHIO S ATE T UNIVERSITY 0 The Ohio State University % ' $ Lecture # 13 & Patrick Roblin T.H.E OHIO S ATE T UNIVERSITY 1 The Ohio State University % ' $ Various Types of FETs a) Junction FET b) MOSFET G a) b) G S 1 111111 0 000000 1111111111 0000000000 1111111111 0000000000 N N 1111111111 0000000000 P 1111111111 0000000000 1000000000 0111111111 Si 1111111111 0000000000 P 11111111 00000000 11111111 00000000 N 11111111 00000000 11111111 00000000 S SiO 2 D P G ) S D B G D d) G S D 111111 000000 000000 111111 000000 111111 11111 00000 11111 00000 11111111 00000000GaAs 11111 00000 11111111 00000000 N 11111111 00000000 AlGaAs 11111111 00000000 11111111 00000000 1111111 0000000 N 1111111 0000000 1111111 0000000 GaAs N 2DEG SI GaAs i GaAs c) HEMT d) MESFET FETs were not the rst transistors developed but MOSFETs are now the most widely used in ICs. & Patrick Roblin 2 T.H.E OHIO S ATE T UNIVERSITY The Ohio State University % ' $ The Junction Field E ect Transistor G GATE P+ DRAIN N D P+ ID CHANNEL R Space Charge SOURCE S VG = VGS=0 Space Charge GATE 1/R G ID + VDS − VDS The gate is grounded A resistive channel is formed between source and drain & Patrick Roblin T.H.E OHIO S ATE T UNIVERSITY 3 The Ohio State University % ' $ Non-Linear Resistance as a function of VDS G P+ DRAIN D GATE ID CHANNEL N P+ VGS=0 SOURCE S GATE 1/R G ID + VDS − VDS The drain to gate voltage VDS increase reverse biasing the junction Consequently the channel width reduces as VDS is increased OHIO This increases the channel resistance S ATE T & Patrick Roblin T.H.E UNIVERSITY 4 The Ohio State University % ' $ Non-Linear Resistance for di erent VGS G P+ GATE ID CHANNEL N D VGS=0 S VGS=−1 P+ + G + VGS=−2 −+ ID GATE − VGS=−3 VGS=−4 VDS − VGS VDS A negative gate voltage VGS reverse biased the P N junctions The linear and non-linear resistance increases We can control the drain current with the gate voltage VGS OHIO S ATE T + & Patrick Roblin T.H.E UNIVERSITY 5 The Ohio State University % ' $ Pincho and Saturation G P+ ID (SAT) GATE IDSS ID VGS=0 V N CHANNEL D S VGS=−1 P+ + G + VGS=−2 −+ ID GATE − − VGS VDS VGS=−3 VGS=−4 V V V V VGS=−5=−V P VDS Pincho occurs when the channel closes at the drain The channel closes when VGD = ;VP (Pincho voltage) & ID (SAT ) ' IDSS Patrick Roblin VG ! 1+ VP 2 6 for ; VP < VGS < 0 T.H.E OHIO S ATE T UNIVERSITY The Ohio State University % ' $ Pincho Voltage G P+ ID (SAT) GATE IDSS ID VGS=0 V Depletion D S VGS=−1 P+ + G + VGS=−2 −+ ID GATE − − VGS VDS VGS=−3 VGS=−4 V V V V VGS=−5=−V P The channel is completely closed when VGD = VGS = ;VP (Pincho voltage) No current is owing & Patrick Roblin 7 VDS T.H.E OHIO S ATE T UNIVERSITY The Ohio State University % ' $ Saturation G P+ ID (SAT) GATE IDSS ID VGS=0 V VGS=−1 V VGS=−2 VGS=−3 VGS=−4 V N CHANNEL D ∆ VDS P+ ∆ VDS GATE + G + −+ ID S − − VGS VP V V VDS VGS=−5=−V P V Pincho occurs for VGD (SAT) = VGS ; VDS (SAT) = ;VP ) VD (SAT) = VGS + VP As the drain voltage is increased such that VGD < ;VP the channel is pinched o earlier in the FET channel. The excess voltage VDS = VDS ; VDS (SAT) is dropped OHIO S ATE T across the saturation region DS & Patrick Roblin T.H.E UNIVERSITY 8 The Ohio State University % ' $ Calculation of Pincho Voltage The pincho voltage VP is the reversed biased diode voltage VDG verifying W (x = L) = a: v u 2 (V ; V ) v 2 V u u u DG GD t W (x = L) = 't =a 0 It results that VP = qa2 Na 2 qNd qNd + VGD P+ − + G GATE − W 2a D VGS Z 2h S W ID P+ & Patrick Roblin GATE VxS G VDS T.H.E x L 9 x 0 OHIO S ATE T UNIVERSITY The Ohio State University % ' $ Calculation of the IV Characteristics + P+ − + G VGD GATE − W 2a D VGS Z 2h S W ID P+ GATE VxS G VDS x x L 0 dV 2h(x) Z ID = ; E 2h(x) Z = dx with h(x) = a ; W (x). & Patrick Roblin T.H.E OHIO S ATE T UNIVERSITY 10 The Ohio State University % ' $ Calculation of the IV Characteristics Integrating ID = dV 2h(x) Z dx we get: 2 4 ID = G0VP 6 VDS + 2 VP with G = 2a Z=L !3=2 VGS ;V 3 P 0 13=23 5 ; 2 @ (VDS ; VGS ) A 7 3 VP 0 In saturation we have VGD = ;VP and the current is: 2 ! = 13 ID (SAT) = G VP 4 VDS + 2 ; VGS + 3 5 VP 3 VP 32 & Patrick Roblin 0 T.H.E OHIO S ATE T UNIVERSITY 11 The Ohio State University % ' $ Attributes of Long Channel JFET IV Characteristics ID ID (SAT) V V VGS=−2 VGS=−3 VGS=−4 VG !2 VGS=0 VGS=−1 IDSS V V V ID (SAT ) ' IDSS 1 + V VP VGS=−5=−V P P The transconducance gm(SAT ) increases linearly with the gate VDS voltage: @ID (SAT ) ' 2IDSS 1 + VG ! gm(SAT ) = @V VP VP GS This is only observed in long channel (L > 1 m) devices! & Patrick Roblin 12 T.H.E OHIO S ATE T UNIVERSITY The Ohio State University % ' $ MESFET S G D Schottky N 111111111 000000000 N Depletion 111111111 000000000 111111111 000000000 Channel SI GaAs & Using a Semi-Insulating (SI) substrate and a Schottky junction OHIO we S realize a JFET called the Metal Semicondutor FET (MESFET).TATE Patrick Roblin T.H.E UNIVERSITY 13 The Ohio State University % ' $ Lecture # 14 & Patrick Roblin T.H.E OHIO S ATE T UNIVERSITY 14 The Ohio State University % ' $ Metal Insulator Semiconductor (MIS) Capacitor MOSFET Metal Oxide Semiconductor is a special case of MISFET. MOSFET were rst demonstrated in 1960 by Kahng (OSU alumnus) and Atalla at Bell Lab. G S metal N+ poly Si SiO2 n channel N+ & Patrick Roblin Depletion D metal N+ P body MOS Capacitor 15 T.H.E B OHIO S ATE T UNIVERSITY The Ohio State University % ' $ MOS Capacitance Assume an ideal MOS structure with equilibrium) m = s (already in (V = 0) q φm Ec q φs Ei EFm & Patrick Roblin 10000000 01111111 11111111 00000000 11 00 1 0 11 00 11 Metal 00 Oxide 11 00 16 EFs 1 1111111 0 0000000E 11 00 1 0 1 0 11 00 11111111 00000000 1 0 Semiconductor 11 00 1 0 11 00 1 0 v T.H.E OHIO S ATE T UNIVERSITY The Ohio State University % ' $ Accumulation Holes are accumulated at the oxide semiconductor interface ε V<0 Ec E Fm Ei −qV EFs Ev & Patrick Roblin M O S T.H.E OHIO S ATE T UNIVERSITY 17 The Ohio State University % ' $ Depletion Holes are depleted at the oxide semiconductor interface V>0 ε Ec Ei EFs Ev −qV & Patrick Roblin Depletion EFm M O S T.H.E OHIO S ATE T UNIVERSITY 18 The Ohio State University % ' $ Inversion Electrons (2DEG) appear at the oxide semiconductor interface V>0 ε Inversion Ec Ei EFs Ev −qV & Patrick Roblin Depletion EFm T.H.E M O S OHIO S ATE T UNIVERSITY 19 The Ohio State University % ' $ Threshold for Inversion ε V>0 Inversion Ec qV i qV S qφ F qφ F Ei EFs Ev qV =V T GS Qd(inv) EFm & Patrick Roblin M O S 0 di x W max T.H.E OHIO S ATE T UNIVERSITY 20 The Ohio State University % ' $ Calculation of VT Ei ; EFs = kT Ln Na F= q q ni Breakup of the applied gate voltage in components: VGS = Vi + VS ) VT = Vi(inv) + VS (inv) with kT Ln Na VS (inv) = 2 F = 2 q ni Let us calculate the electric eld sustained by the depletion region: Z1 dE = ) E (1) ; E (0+) = ) E (0+) = ; Qd(inv) dx s 0 s At the oxide semicondutor interface we have: i E (0;) = s E (0+) & Patrick Roblin s T.H.E OHIO S ATE T UNIVERSITY 21 The Ohio State University % ' $ Calculation of Vi The potential drop across the oxide at inversion is then: di s Vi(inv) = diE (0;) = di E (0+) = ;Qd(inv) i i with Ci = i the oxide capacitance. di ;Qd(inv) = Ci Let us relate the potential drop in the semiconductor VS to Wmax the depletion width: v u 2 V (inv) u sS d V = qNa ) V = 1 qNa W t S max ) Wmax = dx 2s qNa s The depletion charge is then: q Qd(inv) = ;qNaWmax = ;2 q sNa F The threshold voltage is then: Qd(inv) + 2 OHIO VT = Vi(inv) + VS (inv) = ; F S ATE T 2 2 2 & Patrick Roblin T.H.E Ci 22 UNIVERSITY The Ohio State University % ' $ Doping Dependence of VT Qd(inv) + 2 VT = Vi(inv) + VS (inv) = ; C F i v u N 2u kT N = t s NakT Ln a + 2 Ln a Ci ni q ni The larger the p-doping (Na) the larger the threshold voltage required to induce inversion. & Patrick Roblin T.H.E OHIO S ATE T UNIVERSITY 23 The Ohio State University % ' $ Lecture # 15 & Patrick Roblin T.H.E OHIO S ATE T UNIVERSITY 24 The Ohio State University % ' $ Variation of Space Charge with Surface Potential VS 1 10 exp(qVs /2kT) exp(−qVs /2kT) Strong inversion 0 10 Accumulation −1 electrons holes 10 Qs Ionized acceptors 2φF s Q (C/m3 −2 10 −3 10 Vs Weak Depletion inversion ps < Na ns < Na −4 10 ps > Na ns > Na −5 10 φF −6 10 −0.6 & −0.2 0 qLD ; qVs e kT 0.2 φ (V) 0.4 0.6 0.8 1 1.2 S Qs jE (0+)j = Patrick Roblin q = sE (0+) (2)kT " −0.4 Vs + qVs kT ;1 ; p n0 25 0 qVs e kT qVs ; kT ; 1 # with s T.H.E LD OHIO = s2kT S ATEp0 Tq UNIVERSITY The Ohio State University % ' $ Charge Distribution in the MOS Capacitor V>0 ε Qn Inversion Ec Qm qV S qφ F qφ F Charge per unit area Ei EFs Ev qVGS=VT Qd(inv) W max 0 d −i EFm M & Patrick Roblin O S 0 di x W max x Qd Qn T.H.E OHIO S ATE T UNIVERSITY 26 The Ohio State University % ' $ Capacitance of the MOS Capacitor Qm Qm Charge per unit area Charge per unit area Ci Ci W max 0 −i d Qd x Ci Low Frequency Ci Cd W max 0 d −i C Qn Qd Qn Low Frequency x Ci Cd Ci +Cd V High Frequency & Patrick Roblin High Frequency T.H.E OHIO S ATE T UNIVERSITY 27 The Ohio State University % ' $ Capacitance of the MOS Capacitor At low frequencies (< 100 Hz) the minority carriers have the time to move across depletion region to update the surface charge. The MOS capacitance is then: Ci = i di At high frequencies (>1 MHz) only the charge in the depletion has the time to be updated. The capacitors Cd = s=Wmax and Ci = i=di are then in series and the MOS capacitance is: CiCd Ci + Cd In a MOSFET the update charge will come through the channel and the capacitance will be at both low and high frequencies: Ci = i OHIO & Patrick Roblin T.H.E di S ATE T UNIVERSITY 28 The Ohio State University % ' $ Real material with di erent work-function q φ s −q φ m V=0 V<0 ε 000000 111111 000000 111111 11 00 1 0 11 00 11 00 −qV= 11 00 11 00 q φ −q φ 11 00 11 00 11 00 11 00 11 00 11 00 Metal 00 Oxide 11 EFm Inversion q φs q φm Ec Ei s EFm EFs Ev M O Depletion S Flat band is achieved for V = VFB = & Patrick Roblin Ec Ei m m; s = ms EFs 1 00000000 E 11111111 11 00 11111111 00000000 1 0 11 00 11111111 00000000 1 0 Semiconductor 11 00 1 0 11 00 1 0 v <0 T.H.E OHIO S ATE T UNIVERSITY 29 The Ohio State University % ' $ N+ Poly on N and P Silicon 0 −0.2 −0.4 φms (V) −0.6 −0.8 −1 −1.2 n+poly on n−Si n+poly on p−Si −1.4 18 10 19 10 20 21 10 10 Nd,Na (/m3 22 10 23 10 24 10 N+ poly-crystaline Silicon is used instead of metal so as to sustain high temperature processing. The Fermi level of N+ poly is at Ec. As the doping varies we obtain di erent ms. OHIO & Patrick Roblin T.H.E S ATE T UNIVERSITY 30 The Ohio State University % ' $ Charges in Oxide Metal Qm Oxide V<0 Na+ Q ot Qi SiOx ++ Semiconductor Ec + + + E + + E +00 11111111 00000000 11 11111111 00000000 111111 000000 111111 000000 111 000 Qi 111 000 −qV= 111 000 Ci 111 000 111 000 111 000 Oxide Metal 00 11 010 1 111 000 EFm Qf Q it Qi Ci i 11 00 00000000 11111111 11 00 00000000 11111111 11 00 Semiconductor 11 00 Fs Ev Mobile charge (e.g., Na+): Qm (small for clean process) Fixed charges trapped in the oxide: Qot Fixed positive charge in SiOx layer with ionic Si due to uncompleted Si bonds: Qf Interface states: Qit (relatively fast states) & Patrick Roblin T.H.E OHIO S ATE T UNIVERSITY 31 The Ohio State University % ' $ Threshold Voltage for Real MOS Capacitors The e ect of the various charges can approximated by positive charges near the interface. The at-band voltage is negative and reduces the threshold voltage: Qi ; Qd(inv) + 2 VT = VT (ideal) + VFB = ms ; F Ci Ci ms is negative ; Qii is negative C (inv) ; QdCi and 2 F are { negative for p channel { positive for n channel & Patrick Roblin T.H.E OHIO S ATE T UNIVERSITY 32 The Ohio State University % ' $ Charge Control Gate ++ + + −Q n ++ + 0 Oxide Qn Qd + L − − − − Inversion− − − x − VT Depletion VGx For VGx above VT the total charge in the semiconductor Qn is given by: Qs = Qn + Qd with Qn the channel charge and Qd the depletion charge. The threshold gate voltage is given by: V = V ; Qd(max) + V & T Patrick Roblin FB Ci T.H.E s OHIO S ATE T UNIVERSITY 33 The Ohio State University % ' $ Charge Control Gate ++ + + −Q n ++ + 0 Oxide Qn Qd − − − − Inversion− − − + L x − VGx VT Depletion Above threshold the gate to channel voltage is given by: VGx = VFB ; Qs + Vs = VFB ; Qn ; Qd + Vs Ci Ci Ci Solving for the channel charge: " Qd + V !# Qn = ;Ci VGx ; VFB ; C s i 2 0 13 Q (max) + V A5 = ;Ci 4VGx ; @VFB ; d s & Patrick Roblin Ci = ;Ci (VGx ; VT ) T.H.E OHIO S ATE T UNIVERSITY 34 The Ohio State University % ' $ IV for Long Channel MOSFET G S metal N+ poly Si SiO2 n channel N+ Depletion D metal N+ P body MOS Capacitor B ID = ; nZQn dVxS dx ZL Z VDS ID dx = ZCi (VGS ; VxS ; VT ) dVxS 0 & 0 1 V # where k = ZCi ID = kN (VGS ; VT )VDS ; 2 DS N L Patrick Roblin " 2 T.H.E OHIO S ATE T UNIVERSITY 35 The Ohio State University % ' $ IV for Long N-Channel MOSFET " 1V # ID = kN (VGS ; VT )VDS ; 2 DS ID 2 ID (SAT) Patrick Roblin V VGS=4 & VGS=5 V VGS=3 VGS =2 VGS 1 = V VGS= 0=V 36 V V T VDS T.H.E OHIO S ATE T UNIVERSITY The Ohio State University % ' $ IV for Long P-Channel MOSFET G S metal N+ poly Si SiO2 n channel P+ Depletion D metal P+ N body MOS Capacitor VGS = 0=VT B ID V DS V = −1 V GS V =−2 V GS V = −3 V GS V S =−− V 4 G & Patrick Roblin VGS =−5 V T.H.E OHIO S ATE T ID (SAT) UNIVERSITY 37 The Ohio State University % ' $ Current in Saturation Saturation occurs for VGD = VT . Therefore replacing VDS = VGS ; VT in the FET IV: " 1V # ID = kN (VGS ; VT )VDS ; 2 DS we get: 2 ZC ZC ID (SAT) = 2L i (VGS ; VT ) = 2L i VDS 2 2 The MOSFET transconductance is then: @ID (SAT) = ZCi (V ; V ) gm(SAT) = GS T & @VGS L gm varies linearly with the gate voltage. Patrick Roblin T.H.E OHIO S ATE T UNIVERSITY 38 The Ohio State University % ' $ Equivalent Circuit and Unity Current Gain Cuto Frequency !T Gate Drain + vgs gm vgs Cg − Source Source The unity current gain cuto frequency is obtained from: gm = 2 (V ; V ) jgmvgsj = jj!T Cgsvgsj ) !T = 2 GS T Cgs L 2 !T is inversely proportional to the square of the gate length L in long channel devices (L > 1 m). & Patrick Roblin T.H.E OHIO S ATE T UNIVERSITY 39 The Ohio State University % ' $ Lecture # 16 & Patrick Roblin T.H.E OHIO S ATE T UNIVERSITY 40 The Ohio State University % ' $ Device Scaling To avoid breakdown and velocity saturation, the device dimension and voltages should be scaled at the same rate K. surface dimension (L Z ) 1=K vertical dimension (di xj ) 1=K Impurity concentrations (Na Nd) K Current, Voltages (ID VDS VGS ) 1=K Transconductance (gm) 1 Power dissipation 1=K Power Density 1 Electric eld 1 OHIO 2 & Patrick Roblin T.H.E S ATE T UNIVERSITY 41 The Ohio State University % ' $ Short Channel E ects Velocity saturation Drain induced barrier lowering (depletion regions of source and drain joins leading to a variation of the threshold voltage) Hot electron e ects (high longitudinal electrical elds leads to trapped electrons of the oxide which induce a threshold voltage shift) Parasitics bipolar transistor (high longitudinal electrical elds create electron hole pairs which activate the parasitic BJT). Gate induced drain leakage (high transverse electric elds in drain leads to interband tunneling from valance to conduction band) OHIO & Patrick Roblin T.H.E S ATE T UNIVERSITY 42 The Ohio State University % ' $ Charge Sharing in Short Channel MOSFET G S metal N+ D N+ poly Si SiO2 n channel metal 11 00 111 000 11 00 111 000 11 00 111 000 Depletion 11 00 111 000 N+ P body B G S N+ poly Si SiO2 n channel metal N+ D metal N+ Depletion P body & B Leads to a reduction of the threshold voltage VT . Patrick Roblin T.H.E OHIO S ATE T UNIVERSITY 43 The Ohio State University % ' $ Velocity Saturation µF vd vs = µF c Fc F Velocity saturation arise due to the heating of the carriers by Joule e ect which in turns decreases their mobility. FC is on the order of kV/cm and vS about 107 cm/sec. OHIO S ATE T Short channel transistors usually operate in the regime of velocity saturation. & Patrick Roblin T.H.E UNIVERSITY 44 The Ohio State University % ' $ Field and Potential in the MOSFET Channel Zx Z VxS (x) (VOUT ; VxS )dVxS 1 xID = (VOUT )VxS (x) ; 2 VxS (x) where we have introduced = Z CG and VOUT = VGS ; VT . The channel potential VxS measured from the source S is given by v u 2xID = 0 ) V (x) = V ; uV ; 2xID t V ; 2V V + 0 ID dx = 0 2 2 xS xS OUT xS OUT 2 OUT The longitudinal electric eld in the channel is then & dVxS = ; r ID F (x) = ; dx VOUT ; Patrick Roblin 2 xID 2 : T.H.E OHIO S ATE T UNIVERSITY 45 The Ohio State University % ' $ Saturation in Short Channel MOSFETs In short channel devices current saturation occurs when the channel eld at the drain side x = Lg reaches the critical eld Fc F (Lg ) = ; r IDS VOUT ; 2 = ;Fc Lg IDS 2 We can rewrite this equation v u u2 tVOUT ; 2Lg IDS IDS = Fc IDS + ( Fc 2Lg )IDS ; Fc VOUT = 0 The positive saturation drain current IDS solution is then q IDS = ; Fc Lg + ( Fc Lg ) + Fc VOUT 2 & Patrick Roblin 2 2 2 2 2 2 2 2 2 2 T.H.E OHIO S ATE T UNIVERSITY 46 The Ohio State University % ' $ Transconductance of Short Channel MOSFETs The transconductance in saturation is then given by @I gm(SAT ) = @VDS = s VOUT (1) GS Lg 1 + VOUTg Fc L For large gate voltages VGS , the saturation drain current becomes IDS ' FcVOUT = Z FcCG(VGS ; VT ) (2) where CG = d is the gate capacitance per unit area (see Chapter 8). 2 22 2 2 The maximum transconductance in saturation is then given by @IDS = F = Z C F = Zv C (3) gm MAX (SAT ) = @V c Gc SG GS The maximum transconductance gm MAX (SAT ) of a short channel & MOSFET/MODFET in saturation is seen to be a constant. Patrick Roblin T.H.E OHIO S ATE T UNIVERSITY 47 The Ohio State University % ' $ Short Channel MOSFET IV Characteristics ID & Patrick Roblin V GS =7 V GS =6 V GS =5 V GS=4 V GS=3 V GS=2 V GS 1 = V V V V V V V V GS= 0=V T V DS T.H.E OHIO S ATE T UNIVERSITY 48 The Ohio State University % ' $ E ective Channel Length Reduction As the drain voltage is increased, the critical eld is reached earlier in the channel: L ! Leff = L ; L. G P+ IDSS vs D ∆L L eff VGS=0 V VGS=−1 V VGS=−2 VGS=−3 VGS=−4 V S ∆ VDS GATE + G + −+ ID Patrick Roblin ID N CHANNEL P+ & ID (SAT) GATE − VDS − VGS VP V V VDS VGS=−5=−V P T.H.E OHIO S ATE T UNIVERSITY 49 The Ohio State University % ' $ Equivalent Circuit and Unity Current Gain Cuto Frequency !T Gate Drain + vgs gm vgs Cg − Source Source The unity current gain cuto frequency is obtained from: gm !T = 2 Cgs !T is inversely proportional to the square of the gate length L in long channel devices (L > 1 m). !T = 2 L (VGS ; VT ) !T is inversely proportional to the gate length L in short channel devices (L < 1 m). OHIO !T = 2 v S S ATE T L 2 & Patrick Roblin T.H.E UNIVERSITY 50 The Ohio State University % ' $ High Electron Mobility Transistor Energy Ec Ec Ec Ec EF Ev Ev + n AlGaAs iGaAs EF Ev Position Ev a) b) S G D 11111 00000 11111 00000 11111111 00000000GaAs 11111 00000 11111111 00000000 N 11111111 00000000 AlGaAs 10000000 01111111 00000000 11111111 GaAs & Patrick Roblin 2DEG i GaAs T.H.E OHIO S ATE T UNIVERSITY 51 The Ohio State University % 332 I --V model of the MODFET (V) V C 0.40 0.1 0.32 0 0.24 –0.1 0.16 0.08 –0.2 –0.3 x (m) (a) N 0 0.5E-6 1E-6 (/cm2) S 1E12 8E11 6E11 V =0 (V) D 4E11 2E11 0.4 0 x (m) (b) 0 0.5E-6 1E-6 (V/m) EC 4E6 0.4 3E6 2E6 1E6 0 V =0 (V) D –1E6 x (m) (c) 0 0.5E-6 1E-6 Fig. 10.8. Plot of: (a) the channel potential, (b) the channel 2DEG charge and (c) the channel electric field versus position for various drain-to-source voltages. (Y. M. Kim and P. Roblin, IEEE Transactions on Electron Devices, Vol. ED-33 No. 11, pp. 1644–1651, 1986. c 1986 IEEE.) 332 I --V model of the MODFET (V) V C 0.40 0.1 0.32 0 0.24 –0.1 0.16 0.08 –0.2 –0.3 x (m) (a) N 0 0.5E-6 1E-6 (/cm2) S 1E12 8E11 6E11 V =0 (V) D 4E11 2E11 0.4 0 x (m) (b) 0 0.5E-6 1E-6 (V/m) EC 4E6 0.4 3E6 2E6 1E6 0 V =0 (V) D –1E6 x (m) (c) 0 0.5E-6 1E-6 Fig. 10.8. Plot of: (a) the channel potential, (b) the channel 2DEG charge and (c) the channel electric field versus position for various drain-to-source voltages. (Y. M. Kim and P. Roblin, IEEE Transactions on Electron Devices, Vol. ED-33 No. 11, pp. 1644–1651, 1986. c 1986 IEEE.) 332 I --V model of the MODFET (V) V C 0.40 0.1 0.32 0 0.24 –0.1 0.16 0.08 –0.2 –0.3 x (m) (a) N 0 0.5E-6 1E-6 (/cm2) S 1E12 8E11 6E11 V =0 (V) D 4E11 2E11 0.4 0 x (m) (b) 0 0.5E-6 1E-6 (V/m) EC 4E6 0.4 3E6 2E6 1E6 0 V =0 (V) D –1E6 x (m) (c) 0 0.5E-6 1E-6 Fig. 10.8. Plot of: (a) the channel potential, (b) the channel 2DEG charge and (c) the channel electric field versus position for various drain-to-source voltages. (Y. M. Kim and P. Roblin, IEEE Transactions on Electron Devices, Vol. ED-33 No. 11, pp. 1644–1651, 1986. c 1986 IEEE.) ...
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This note was uploaded on 01/11/2012 for the course ECE 432 taught by Professor Lu during the Fall '08 term at Ohio State.

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