ex1_sol_s11

# ex1_sol_s11 - EEL3701 — Dr Gugel NAME K6 9 Spring 2009...

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Unformatted text preview: EEL3701 — Dr. Gugel NAME K6 9 Spring 2009 Exam #1 UF ID# W W W 0 Open book and open notes, 90-minute examination. No eiectronr'c devices are permitted. 0 All work and solutions are to be written on the exam where appropriate. Page 1) 7 points Page 2) ‘ 16 points Page 3) 20 points Page 4) 1? points Page 5) 20 points Page 6) 20 points TOTAL of 100 Re-grade Requests — Must be handed in the day exams are returned to students: problémit ,. brieS- .{ZSQYI‘ {on 130 pm— WK‘TE ON THE ’ OTHER P9555 no THE new 1. Perform the following binary additions and subtractions by hand. Show all your work below. Assume the numbers are all unsigned binary. (2,2,3 pt.) 10101 610l7’ 10101010 10101001 1010.101 10111011 ~10010010 X0100.010 +10001111- 000101 H Ilill0loa lololbtl ’7 1‘ 'o‘\010\ rel ‘ “0 //»——_—» lb [onshooio' Page 1 . Page Score = 2. Given the foliowing logic truth table, simplify with the K-Map below into Minimum Sum of Products (M80?) and Minimum Product of Sums (MPOS). (8 pt.) ABCD Y 0000 1 0001 1 0010 0 0011 0 0100 1 0101 1 0110 X 0111 1 1000 0 1001 X 1010 0 1011 1 1100 X 1101 X 1110 1 1 1111 Y (MSOP) = M v (MPOS) = W (A+8+€) C £13m) (34640) 3. Simpiify the equation below with De Morgan’s Rule and Boolean Identities to ﬁnd a MSOP. (8 pt.) ,] Y= [A1C)[A*B)[A*B*C) Y= PV—Hng‘ Q MSOP Page 2 Page Score = 4. Directiy synthesize a circuit for the foliowing equation using only 2 Input NOR gates. (10 pt.) Y = ( W+X ) ( W +2) ;Y.H, w.L, x.L. Z.H Do Not Simplify the Equation! 5. Given the 4 bit magnitude comparator below. Find the logic equation for 2H. (10 pt.) iA>B W.L L Z.H ..... A=B 4bitMag Comparator iA=B . ._ X.H H A<B iA<B (—m Y.L L BB 32 BI BO A3 A2 A1 A0 i MLLGND HLLGND CHD.L E.LF.L ED L, L LL 5?, CD H L H L 5?. CE H H H H E? Z“: WMCQDEH CDEH CDEF +CDE? 3 Page 3 Page Score = 6. Find the iogic equation for AH, BL and Y. L. SIMPLIFY IF NECESSARY. (4, 5, 2 pt.) Dual 4-:1 MUX 7. In the circuit for #6, if we remove the puli-up resistor, what is the new equation for Y.L? (3 Pt.) Y.L= E C®b omag WTNKVtOtONr‘EgLL;F whit/his ”75335— (SHEET) 8. In the circuit for #6, if you swap the pull-up resistor with a pull—down, what is the new Y.L? ( Pt.) Y.L= L (“1””“325 low!) Page 4 Page Score = 9. You are given as many Tri—state buffers with high true enables, Tri-state buffers with low true enables and putt—up, pull-down resistors as needed and no other gates. Build a 2:4 decoder with high true inputs and outputs. The best design will receive the most points. (10 pt.) 10. Derive the iogic equation for the following circuit below. Show all intermediate terms as both high and low signals. DO NOT SIMPLIFY. (10 pt.) E 9‘ (E 1)); ll." (ET-DJ" ,- Page 5 Page Score = 11. Design a circuit that multiplies a 3 bit signed number by -2. Le. compute N x —2 where N is a 3 bit signed input. Show the block diagram for the device and show the circuits for the most signiﬁcant bit and least signiﬁcant bit. The best design receives highest points. (14 pt.) ....3) P4“) 12. For the Nest State Table below, draw the corresponding State Diagram. Assume the. design is based on a simple counter consisting of (3) D Flip-Flops and a corresponding logic block. (6 pt.) Q2 Q1 00 D2 D1 130 001 011 010-100 @ 011 101 ® 2, 7 100 110 , 101 111 b g) L®J 110 000 111 001 Page 6 Page Score = ...
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