ex2_sol_s11 - . / EEL3701 — Dr. Gugei Last Name ‘ First...

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Unformatted text preview: . / EEL3701 — Dr. Gugei Last Name ‘ First lg Spring 2011 Exam 11 UP !D# - Open book and open notes, 90-minute examination to be done in pencii. ' No electronic devices are permitted or needed. - All work and solutions are to be written on the exam where appropriate. Point System (for instructor and TA use only) Page 2) 18 points 6am" Page 3) 14 points ! 1km” Page 4) , 12 points a ‘9 mm“ 1"" Page 5) 25 points Page 6) 18 points T05 I“ Page 7) ' 13 points flax/LL- TOTAL ' out of 100 Grade Review Information: (NOTE: deadline of request for grade review is the day the exam is returned.) 1. Given the foilowing ASM Diagram answerthe questions that foiEow. States: 32:0 Inputs: W.L Outputs: A.H, B.L 1A. Draw a functional block diagram on the lower right to implement the design. Assume D Flip-flops are used and label your present states Qn...QO as needed. (6 pt.) (12 pt.) 10. Show the logic equation and required circuit for WM (least significant state flip-flop input). Assume only NOR gates are available to implement the circuit and the logic equation should be in MSOPfon‘n. (7 pt.) F _____ / ___ 1, WQiq'Q‘QO $&l(w+ b are available to implement the circuit and the logic eq ation should be in MSOP form. (7 pt.) 1D. Show the logic equation and required circuit to? (tow true output). Assume only NOR gates 61’ Page 3 Page Score = 1E. instead of using a CPLD, assume that the design will be implemented in a 16K x 8 EPROM. All un-used address lines should be tied high. Show the EPROM connections below (left) and the memory contents (right). Recall that several of the input & output signals are low true. (4 pt, 8 pt.) {bk :9 zit-2’0: 2W mam Anomex) DATA(H_e>5) ?FF8 :LHLH 5 ‘ BFF 0: 'HL’HL A ‘ MUX Select $3 = 0,1N7:O => *Mux Out 53 = 1, REGC (27:0 => *Mux Out *When —OE_M = 1, else if—OE_M = 0 then Mux Out = Hi 2 [tri—state]. REG A/B Signals —LD_A/B = load data from D7:G -OE_A : output data onto 137:0 ALU Function HHOQHHOO§U§ 5H HOP—\Ol—‘CDl—‘OLG .0 OUT : IN1 OUT = INZ OUT = IN1 PLUS 1N2 OUT = Complement (IN1) OUT = [N1 multiplied by 2 OUT = IN1 divided by 2 OUT = IN1 PLUS 1 OUT = [N1 MINUS 1 Hl—‘l—‘I—‘DOOOLG CLK Page 4 Page Score = 2A. Assuming that four DIP switches will be used to simulate an instruction register (IR3:O), draw the components inside the new controller block in the CPU that will be used to generate all the register and mux input signals shown on the previous page. Assume that the controller will be implemented in a EPROM and that there are 29 states in the Controller ASM Diagram. (7 pt.) 1» 28. Given the following instructions below, creatan AS Diagram for the Controller block. in the ASM Diagram states, show only the ALU & Register signals that are true for a particular state. The |R3:0 bits will be switched by hand during the first state in the ASM and therefore are inputs to your controller. (3, 9, 6 pt.) lR3:O = 0; ln7:0 => RegA IR3:0 = 1; Average (RegA, RegB) => Reg A IR3:O = 2; RegA + 1 => RegA Page 5 Page Score = . ' 20. Show how the components & design required to create the Least Significant Bit of RegA. (6 pt.) 3A. You are given a CPU with A15:0, D1510, Rl—W and —DS (data strobe). The reset vector is at 9FFF Hex. i.e. After reset, this is where the address of the first instruction is fetched from memory. Implement in the system an 8K block of EPROM and 16K block of SRAM with the following available devices: 8K x 8 EPROMs and 32K x 16 SRAMs. Place the SRAM block in the highest 16K of memory and the EPROM block where it is needed for the reset vector. Draw the EPROM and SRAM blocks below and label all connections. (12pt.) :> ZL/\Zm=;>fll3:o 7 32K f” I3. 3 fl/ZIO Mp C réi’fl WV 13 ’5 film 0 WV D716 Page 6 Page Score = ~ '33. Show the memory ranges for each biock of memory (EPROM and SRAM) and the required decode circuitry for each memory device. Make sure your signals in the decode circuit match those shown on your memory dewces on the prevnous page. (8 pt.) ’t 6mm COnoJFF? 5mm 7* 5mm 800m QFFFfQK tid— m flowwEFFF / €14 :. 51/9. ,4/4. I‘M 30. What data and address must be programmed in the EPROM to facilitate the RESET Vector? Le. At what location in the EPROM and what data vaiue needs to be programmed such that the CPU will fetch the iowest address of the EPROM (1St instruction in ROM) after Reset. (5 pt.) a: a 3 EPROMAddresswei/iceis notpluggedintheboard) Hex Data Hex - (2V ; Data. (mum Efflom Dab.» gig/"(v f”! W‘I’m 019,511+ Page 7 Page Score = ...
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ex2_sol_s11 - . / EEL3701 — Dr. Gugei Last Name ‘ First...

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