FoLD_5th_ch7

# FoLD_5th_ch7 - gates are xample of aird levels 7.2 7.3 7.4...

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Unformatted text preview: gates are xample of aird levels 7.2 7.3 7.4 7.5 7.6 7.7 7.8 7.9 7.10 Multi—Level Gate Circuits / NAND and NOR Gates 197 Realize the following functions using AND and OR. gates. Assume that there are no restrictions on the number of gates which can be cascaded and minimize the number of gate inputs. (a) AC’D + ADE’ + BE’ + BC’ + A’D’E' (b) AE + BDE + BCE + BCFG + BDFG + AFG Find eight different simpliﬁed two-level gate circuits to realize F(a, b, c, d) = a’bd + ac’d ' Find a minimum three-level NAND gate circuit to realize F(A, B, C, D) = 2 m(5, 10, 11, 12, 13) (four gates) Realize Z = A’D + A’C + AB’C’D’ using four NOR gates. Realize Z = ABC + AD + C’D using only 2—input NAND gates. Use as few gates as pos- sible. Realize Z = AE + BDE + BCEF using only 2—input NOR gates. Use as few gates as possible. (a) Convert the following circuit to all NAND gates, by adding bubbles and inverters where necessary. (b) Convert to all NOR gates (an inverter at the output is allowed). A, B C E Z D’ F 0/ Find a two—level, multiple-output AND—OR gate circuit to realize the following functions. Minimize the required number of gates (six gates minimum). f1 = ac+ad+b’d and. 'f2 = a’b’ +a’d'+cd’ Find a minimum two—level, multiple-output AND—OR gate circuit to realize these functions. f1(a, b, c, d) = 2m(3, 4, 6, 9, 11) f2(a, 17. c, d) = 2m(2,4,8,10, 11,12) f3(a, b, c, d) = 2 m(3, 6, 7, 10, 11) (ll gates minimum) . i l 1 . 1 98 Unit 7 R—AND circuit to simultaneously realize = 2 m(2, 3, 8, 9, 14,15) 5, 8, 9,14,.15) —level 0 Fl(a5 b: cad) F2(a! 17: ca d) = 2 ma), 1, 7.1 1 Find a minimum two (minimum solution has eight gates) alize the functions given in Equations (7-23) 7 .12 Find a minimum two—level OR—AND circuit to re on page 193 (nine gates minimum) (a) Find a minimum two—level NAND—NAND circuit to real Equations (7-23) on page 193. (b) Find a minimum two—level NOR—NOR circuit to realize the functions given in Equations (7—23). ircuit to realize ‘ ize the functions given in 7.13 (1 OR gates, ﬁnd a minimum 0 7.14 UsingAND an fill, b, C, d) = M9M1M3M13M14M15 (a) using two—level logic (b) using three—level logic (12 gate inputs minimum) —level circuit to realize (a) F=a’c+bc'd+ac’d (b)F=(b'+c)(a+b’+d)(a+b+c’+d) (c)F=a'cd'+a’bc+ad \ (d)F = a'b+ac+bc+bd’ sume that there are no using, AND and» OR gates. As mize the number of gate s which can be cascaded and mini inputs. (a) ABC' + ACD + A’BC + A'C'D ' (b) ABCE + ABEF + ACD’ + ABEG + ACDE , 7.17 A combinational switching circuit has four inputs , ', iff three or four of the inputs are 0. (a) Write the maxterm expansion for F. (b) Using AND and OR gates, ﬁnd 'a minimum three-level circuit to realize F (ﬁve gates, 12 inputs). —level gate circuits to realize 7 .18 Find eight different simpliﬁed two =(x+y’ +z)(x’ +y+z)w (a) F(w,x,y,Z) (b) F(a, b, c, d) = 2 m(4, 5, 8, 9, 13) m num— = 2 in(0, l, 3, 4, 7) as a two—level gate circuit, using a minimu 7.19 Implement f(x, y, 2) her of gates. (a) Use AND gates and NAND gates. (b) Use NAND gates only. Multi-‘Level Gate Circuits / NAND and NOR Gates 199 7.20 Implement ﬁa, b, c, d) = E m(O, 1, 2, 3, 7, 11, 15) as a two—level gate circuit, using a minimum number of gates. (a) Use OR gates and NOR gates. (b) Use NOR gates only. 7.21 Realize the functions indicated below using a minimum two-level NAND-gate circuit and 15 (7-23) I also using a minimum two-level NOR gate circuit. I (a) Realize the function from Problem 5.4. (b) Realize the function from Problem 5.8(a). (c) Realize the function from Problem 5 .8(b). (d) Realize the function from Problem 5.9(a). (e) Realize the function from Problem 5.9(b). . U (f) Realize the function from Problem 5.22(a). .5 (g) Realize the function from Problem 5.22(b). V given in Equations 7.22 f(a, b, c, d, e) = 2 m(2, 3, 6, 12, 13, 16, 17, 18, 19, 22, 24, 25, 27, 28, 29, 31) (a) Find a minimum two—level NOR—gate circuit to realize f. (b) Find a minimum three—level NOR-gate circuit to realize f. 7.23 Design a minimum three-level NOR—gate circuit to realize f= a’b’ + abd + acd 7.24 Find a minimum four—level NAND- or NOR—gate circuit to realize (a) Z = abe’f+ c’e'f + d’e’f + gh (b) Z=(a’+b+e+f)(c’+a’+b)(d’+a’+b)(g+h) “ here are no . f ate -- mbero g 7.25 Implement abde’ + a'b’ + c using four NOR gates. 7.26 Implement x'yz + xvy’w’ + xvy’z’ using a three-level NAND-gate circuit. 7.27 Design a logic circuit that has a 4—bit binary number as an input and one output. The output should be 1 iff the input is a prime number (greater than 1) or zero. (a) Use a two—level NAND-gate circuit. (b) Use a tvvo—level NOR-gate circuit. (c) Use only 2—input NAND gates. ut (F). Fp=0 F (ﬁve gates, \ 7.28 Work Problem 7.27 for a circuit that has an output 1 iff the input is evenly divisible by 3 (0 is divisible by 3). 7-29 Realize the following functions, using only 2—input NAND gates. Repeat using only 2—input NOR gates. (a) F = A'BC' + BD + AC + B'CD' I (b) F = A'CD + AB'C'D + ABD' + BC 7?;wa/ji/7/7 200 Unit 7 7.30 (b) Convert your circuit (c) Repeat (b), except conv A[BC’ + D + E(F’ + GH)] using NOR gat gate circuit to realize these functions 7.31 7.32 7.34 7.35 7.36 7.37 7.38 7.39 (a) Find a minimum F(A, B, C, D) = E m(0, 1, 2, Realize Z = Repeat 7 .32 for the following functions ( f1(a,b,c,d) =2m b,c,d) = 2m(0, l, 2,3, 5,7, 8, 10) Repeat 7.32 for the fell (a) Find a minimum two f1 = b’d + a (b) Realize the same func Find a minimum two—level, multiple (eight gates minimum). f1(a,b,c,d) = f2(a,b,c,d) = f3 (a, b. M) = 2 m(4,11,13, f2 (a: circuit of 2-inp 3, to 2—input ut and 2-input OR g 4, 5, 7, 9,11,13,14,15) NAND gates. Add inverters ert to 2—input NOR gates. ' —output AND—OR ates to realize here necessary. 2 m(10, ll, 12, 15) + 2 d(4, 8, 14) 2 m(0, 4,8, 9) + 2 d(l, 10, 12) 14,15) + 2 d(5,9, 12) six gates). (2, 3. 5, 6, 7, 8,10) owing functions (eight gates). f1 (x, y, z) = 2 m(2, 3, 4,5) f2 (x, y, z) = 2 m(1, 3, 5,6) f3 (x, y, Z) = 2 m(l, 2, 4, 5, 6) Repeat Problem 7.35 for f1 = (a) Fin fl : (b) Repeat for a minimum two (a) Find a minimum two—level f1 = 2 m(0, 2, 4, 6, 7, 10, 14) and f2 (b) Repeat for a minimum two Draw a multiple-level, multiple- d a minimum two (a) NAND and AND gates -1eve1, multiple— ’b’ + c’d and f2 = a tions with a minimum two (b) NAND gates only (a direct conversion i ac’ + b’d—l— c -1eve1, multiple—output 6,7, 11,13,14,15) and f2 = —level, NOR—NOR circuit. ‘1 , multiple- -level, multiple—output NOR— output, circuit equiv output OR-AND circuit to realize ’d’ + bc’ + bd’. -leve1 NAND—NAND circuit. ’d and f2 = b'c + a’d + cd’. NAND—NAND circuit to realize 2 m(3, 4,6,11,12,13,14). output NAND—NAND circuit to realize = 2 m(0, 1, 4, 5,7, 10,14). NOR circuit. s not possible) es. Add inverters if necessary, alent to Figure 7-24(a) using: ...
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FoLD_5th_ch7 - gates are xample of aird levels 7.2 7.3 7.4...

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