# hw1_s12 - /(A*B + /C) D) Y = /(A+B) * C E) Z = (/A + /B +...

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University of Florida EEL 3701— Spring 2012 Dr. K. Gugel Dept. of Electrical & Computer Engineering Page 1/1 10-Jan-12 10:24 PM Homework 1 Due: Friday, 01/20/12, see below. Note: HW is due by 4 pm in 230 Larsen Hall (look right as you enter the room). Fundamentals of Logic: 1.1 a, c 1.2 b (convert to decimal and hex) 1.5 b 1.6 b 1.7 a, c, e 1.8 1.11 b 1.15 b 1.17 b 1.18 b 1.27 a,c,e Additional Problems: 1. Design by direct implementation the electronic circuits for equations as he following logic equations using any real 1, 2, or 3 input logic gates. Assume all signals are high true (positive logic) and do not simplify the equations. A) Y = X * [/ (D*/E) + C*/G] B) V = /(A*B*/C) + A*B + C C) X =
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Unformatted text preview: /(A*B + /C) D) Y = /(A+B) * C E) Z = (/A + /B + /C) * (/D + /E) 2. Design by direct implementation the electronic circuits for the following logic equations using any real 1 or 2 input logic gates. Assume the signal definitions as shown below. Do not simplify the logic equation. A) X = /A* /B + A*C ;all signals are high true (positive logic) B) X = /A* /B + A*C ;all signals are low true (negative logic) C) X = /A* /B + A*C ;X.H, A.L, B.H, C.L D) X = /A* /B + A*C ;X.L, A.H, B.L, C.H 3. What should the signal definitions be for the equations in #2, such that the minimal about of hardware (gates) are used assuming we have an abundance of NAND gates? Show the signals definitions and resulting circuitry....
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## This note was uploaded on 01/15/2012 for the course EEL 3701c taught by Professor Gugel during the Spring '05 term at University of Florida.

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