W04_06_ExecCycle - 06 06 The Execution Cycle CSC 230 CPU...

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6 The Execution Cycle 06 The Execution Cycle CSC 230
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CPU activity follows the: FETCH - DECODE – EXECUTE - STORE equence sequence (1) fetch instruction om from memory (5) execute instruction which may (2) update current memory address require Storing a result in memory (4) fetch further data, if required (3) decode instruction 2
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CPU activity follows the: FETCH - DECODE – EXECUTE - STORE equence sequence FETCH-DECODE-EXECUTE 1. fetch instruction from memory 2. update current memory address 3. decode instruction 4. fetch further data, if required 5. execute instruction 6. go to step (1) Registers PC Program counter struction register IR Instruction register MAR Memory Address Register MDR Memory Data Register AC Accumulator 3
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ddress Memory address bus control bus MDR ontrol MAR data bus Processor PC IR Control R 1 R 0 ALU R n1 - n general purpose egisters Connections between the processor and the memory registers 4
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Detailed CPU activity 1) fetch Memory (1) fetch instruction from memory address bus a bus control bus a) address in PC MAR MDR Control MAR dat a b) MAR Address Bus c) read signal Control Bus ) ait for memory PC IR R 1 R 0 d) Wait for memory e) content of location in memory Data Bus ALU R n1 - n general purpose registers f) Data Bus MDR g) MDR IR 5
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Detailed CPU activity 2) update Memory (2) update current memory address a) increment PC MDR Control MAR (ready for next instruction) Î Use the ALU PC IR R 1 R 0 ALU R n1 - n general purpose registers 7
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Detailed CPU activity 3) decode Memory (3) decode instruction ± decode phase looks at MDR Control MAR opcode and operands in the content of the IR PC IR R 1 R 0 decoder ± “Decoder” is a hardware component in the Control unit of the PU ALU R n1 - n general purpose registers CPU 8
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Detailed CPU activity 4) fetch Memory (4) fetch further data, if required MAR, MDR and PC are MDR Control MAR possibly in use here could be more Read PC IR R 1 R 0 There could be more Read cycles to fetch operands ALU R n1 - n general purpose registers 9
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Detailed CPU activity 5) execute Memory (5) execute instruction May involve ALU, plus MDR Control MAR reads and writes to memory PC IR R 1 R 0 ALU R n1 - n general purpose registers 10
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Detailed CPU activity 1. fetch instruction from memory ¾ address in PC MAR ¾ MAR Address Bus ead signal ontrol Bus ¾ read signal Control Bus ¾ Wait for memory ¾ content of location in memory Data Bus ¾ Data Bus MDR ¾ MDR IR 2. update current memory address ¾ increment PC (ready for next instruction) ecode struction 3. decode instruction ¾
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W04_06_ExecCycle - 06 06 The Execution Cycle CSC 230 CPU...

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