W04_07_CPUOrgDataPath1

W04_07_CPUOrgDataPath1 - 07 CPU Organization and Datapath...

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07 CPU Organization and Datapath V.1 CSC 230
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Refresher: Detailed CPU activity 1. fetch instruction from memory ¾ address in PC MAR ¾ MAR Address Bus ead signal ontrol Bus ¾ read signal Control Bus ¾ Wait for memory ¾ content of location in memory Data Bus ¾ Data Bus MDR ¾ MDR IR 2. update current memory address ¾ increment PC (ready for next instruction) ecode struction 3. decode instruction ¾ decode phase looks at opcode and operands 4. fetch further data, if required ¾ MAR, MDR and PC are possibly in use) (, p y ) 5. execute instruction ¾ (may involve ALU, reads and writes to memory) 6. go to step (1)
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Control signals Address lines PC MAR Instruction decoder and control logic Learn how a atapath orks Data MDR R Memory bus atapath datapath works by examining in etails the lines Y IR R0 Constant 4 cessor d details the Fetch – Decode –ExecuteCycle Add MUX Select ernal pr o for a general instruction (not Carry-in ALU XOR Sub control ALU lines R n 1 - () A B Int e ARM or RISC) Z 4
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W04_07_CPUOrgDataPath1 - 07 CPU Organization and Datapath...

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