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W04_07_CPUOrgDataPath1 - 07 CPU Organization and Datapath...

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07 CPU Organization and Datapath V.1 CSC 230
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Refresher: Detailed CPU activity 1 f t h i t ti f 1. fetch instruction from memory ¾ address in PC MAR ¾ MAR Address Bus ¾ read signal Control Bus ¾ Wait for memory ¾ content of location in memory Data Bus ¾ Data Bus MDR ¾ MDR IR 2. update current memory address ¾ increment PC (ready for next instruction) 3 decode instruction 3. ¾ decode phase looks at opcode and operands 4. fetch further data, if required ¾ (MAR, MDR and PC are possibly in use) 5. execute instruction ¾ (may involve ALU, reads and writes to memory) 6. go to step (1)
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Control signals Address lines PC MAR Instruction decoder and control logic Learn how a datapath works Data li MDR IR Memory bus atapath by examining in details the lines Y R0 Constant 4 ocessor d Fetch – Decode – Execute Cycle Add A B MUX Select ernal pro for a general instruction (not Carry-in ALU XOR Sub control ALU lines R n 1 - ( ) Inte ARM or RISC) Z 4
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Example: ADD R1,[R3] (not ARM) ADD R1,[R3] R1
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