W04_08-AddrMode+Ch04CAO

W04_08-AddrMode+Ch04CAO - 08 08 Addressing Modes CSC 230 1...

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8 Addressing Modes 08 Addressing Modes CSC 230 1
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INSTRUCTION FORMATS and DESIGN Instructions always contains: (1) opcode () p (2) one of more bytes for operands ± Mnemonics are used for opcodes (symbolic names) egisters (or other) re used for operands ± Registers (or other) are used for operands ote hat the number of bits for the pcode ± Note that the number of bits for the opcode (operation code) subdivision must be large enough to be able to represent all instructions in instruction set
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3 OPERANDS FORMAT opcode F1 (source) F2 (source) F3 (destination) or peration ( pcode applied n source operands opcode F3 (destination) F2 (source) F3 (source) ± Operation (Opcode) applied on source operands ± Result in destination operand ± F1, F2 and F3 are memory addresses or registers ngth? Î length? DD s 1s 2 d s 1+s 2 ADD d, s1, s2 @ d = s1 + s2 (Most ARM instructions, with registers only as operands)
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2 OPERANDS FORMAT opcode F1 (source) F2 (destination) or opcode F1 (destination) F2 (source) ± one of F1 or F2 is usually a register ± Operation applied on both F1 and F2 ± result in one of them Î length ADD d, s1 @ d = d + s1 , @
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1 OPERAND FORMAT opcode F1 ± usually there is an implicit register or accumulator or constant INCR s1 @ s1 = s1 + 4
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1 OPERAND FORMAT or STACK FORMAT opcode ± need instruction only, assumes there is a stack of operands ± takes top element of the stacks by pop and performs peration operation ± result is stored by pushing on stack again ADD @top-of-stack = top-of-stack + next-on-stack i j i+j k k
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One, Two, Three Operands Machines Consider how the C expression A = B*C + D might be evaluated by each of the one, two, and three-address instruction types. ± Assumptions for this example: Addresses and data words are two bytes in size. Opcodes are 1 byte in size. Operands are moved to and from memory one word (two bytes) at a time. Computer Architecture and Organization by M. Murdocca and V. Heuring © 2007 M. Murdocca and V. Heuring
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a) Three Operands Machines A = B*C + D In a three-address instruction, the expression A = B*C + D might be coded as: ult CA mult B, C, A add D, A, A hich eans: which means: A. multiply B by C and store the result at A. B. Then, add D to A and store the result at address A. Computer Architecture and Organization by M. Murdocca and V. Heuring © 2007 M. Murdocca and V. Heuring
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b) Two Operands Machines A = B*C + D In a two-address instruction, one of the operands is overwritten by the result. Here, the code for the expression A = B*C + D is: oad A load B, A mult C, A add D, A Computer Architecture and Organization by M. Murdocca and V. Heuring © 2007 M. Murdocca and V. Heuring
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c) One Operand (Accumulator) Machines A one-address instruction employs a single arithmetic register in e CPU known as the accumulator The code for the A = B*C + D the CPU, known as the accumulator. The code for the expression A = B*C + D is now: load B mult C add D store A A. The load instruction loads B into the accumulator, B. mult multiplies C by the accumulator and stores the result in the accumulator, C. add does the corresponding addition.
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W04_08-AddrMode+Ch04CAO - 08 08 Addressing Modes CSC 230 1...

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