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W10_17_Pipelining - 17 Introduction to Pipelining CSC CSC...

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17 Introduction to Pipelining CSC 230 Department of Computer Science University of Victoria 1
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Increasing performance 1. break the work in small units 2 h” i h h i li f “ k 2. “push” it through a pipeline of “workers” 3. each “worker” performs a function on one piece of work I 1 I 2 I 3 (a) Sequential execution Time F 1 E 1 F 2 E 2 F 3 E 3 F = Fetch cycle E = Execute cycle 2
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Increasing performance Î Pipelining ( ) S ti l ti Time F 1 E 1 F 2 E 2 F 3 E 3 I 1 I 2 I 3 (a) Sequential execution F = Fetch cycle E = Execute cycle Instruction Execution Interstage buffer B1 (b) Hardware organization fetch unit unit I t ti Clock cycle 1 2 3 4 Time F 1 E 1 F 2 E 2 I 1 I 2 Instruction (c) Pipelined execution 3 F 3 E 3 I 3
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Hardware Organization to support the pipeline Interstage buffers F: Fetch instruction D: Decode instruction + fetch operand E: Execute operation W: Write results B1 B2 B3 F Fetch: read instruction from memory D Decode: decode instruction and fetch source operands E Execute: performed specified operation W Write: store result in destination location 4
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Instruction execution divided into four steps I t t b ff Interstage buffers F: Fetch instruction B1 B2 B3 D: Decode instruction + fetch operand E: Execute operation W: Write results Clock Cycle 1 2 3 4 5 6 7 Time F1 D1 E1 W1 I 1 Instruction F2 D2 E2 W2 F2 D2 E2 W2 F3 D3 E3 W3 I 2 I 3 F2 D2 E2 W2 F2 D2 E2 5 F4 D4 E4 W4 I 4 F2 D2
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Use of an instruction queue F: Fetch i t ti Instruction Queue instruction …. D Di t h/D d D: Dispatch/Decode Unit E: Execute operation W: Write results 6
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Superscalar Operation Example: A processor with two execution units F: Fetch instruction …. Instruction Queue Floating Point Unit D: Dispatch Unit Integer Unit W: Write results Maximum throughput of a pipelined processor is 1 instruction per clock cycle Add multiple processing units for several instructions in parallel in each stage Î superscalar processor 7
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Performance issues Need to execute N processes Each process requires m cycles The N processes require in general: T serial = N x m cycles input output Build a pipeline with m stages ¾ The first item will emerge after m cycles ¾ It will take another N-1 cycles for the last item to emerge 8 for a total of T pipeline = m+N-1 cycles
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Consider the possible speedup 1 serial i li T m N speedup T m N × = = + pipeline If N >> m, then 1 m N speedup m m N × = + 9
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Speedup Î Thus an m stage pipeline can speed-up the processing by a factor of m Provided that there are no disruptions Î no branching! Î Interrupting a pipeline is expensive The state must be restored and the cause of the The state must be restored, and the cause of the interruption dealt with, before it is allowed to continue A lot of ingenuity and hardware are devoted in modern processors exactly to ensure that such interruptions do not happen Ult SPARC II 9 t i li UltraSPARC II – 9 stage pipeline Pentium Pro – 12 stage pipeline Pentium 4 20 stage pipeline (2 pipeline stages in each 10 Pentium 4 – 20 stage pipeline (2 pipeline stages in each
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