W10_17_Pipelining - 17 Introduction to Pipelining CSC CSC...

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17 Introduction to Pipelining SC 230 CSC 230 Department of Computer Science University of Victoria 1
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Increasing performance 1. break the work in small units 2. “push” it through a pipeline of “workers” 3. each “worker” performs a function on one piece of work I I I (a) Sequential execution Time F 1 E 1 F 2 E 2 F 3 E 3 1 2 3 F = Fetch cycle E = Execute cycle 2
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Increasing performance Î Pipelining Time F E F E F E I 1 I 2 I 3 (a) Sequential execution F = Fetch cycle E = Execute cycle 1 1 2 2 3 3 nstruction xecution Interstage buffer B1 b) Hardware organization Instruction fetch unit Execution unit (b) Hardware organization Clock cycle 1 2 3 4 Time F 1 E 1 I 1 Instruction (c) Pipelined execution 3 F 2 E 2 F 3 E 3 I 2 I 3
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Hardware Organization to support the pipeline Interstage buffers F: Fetch instruction D: Decode instruction + fetch operand E: Execute operation W: Write results B1 B2 B3 F Fetch: read instruction from memory D Decode: decode instruction and fetch source operands xecute: performed specified operation E Execute: performed specified operation W Write: store result in destination location 4
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Instruction execution divided into four steps Interstage buffers F: Fetch instruction 1 2 3 D: Decode instruction + fetch operand E: Execute operation W: Write results B1 B2 B3 Clock Cycle 1 2 3 4 5 6 7 Time F1 D1 E1 W1 I 1 Instruction F2 D2 E2 W2 F2 D2 E2 W2 F3 D3 E3 W3 I 2 I 3 F2 D2 E2 W2 F2 D2 E2 5 F4 D4 E4 W4 I 4 F2 D2
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Use of an instruction queue F: Fetch Instruction Queue instruction …. D: Dispatch/Decode Unit E: Execute operation W: Write results 6
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Superscalar Operation Example: A processor with two execution units F: Fetch instruction …. Instruction Queue Floating oint Unit D: Dispatch Unit Point Unit Integer Unit W: Write results ± Maximum throughput of a pipelined processor is 1 instruction per clock cycle ± Add multiple processing units for several instructions in parallel in each stage Î superscalar processor 7 pg pp
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Performance issues ± Need to execute N processes ± Each process requires m cycles The N processes require in general: T serial = N x m cycles put utput Build a pipeline with m stages input output ¾ The first item will emerge after m cycles ¾ It will take another N-1 cycles for the last item to emerge 8 for a total of T pipeline = m+N-1 cycles
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Consider the possible speedup serial T mN speedup m N × == 1 pipeline Tm +− If N >> m, then speedup m N × = 1 9
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Speedup Î Thus an m stage pipeline can speed-up the processing by a factor of m Provided that there are no disruptions Î no branching! Î Interrupting a pipeline is expensive he state must be restored and the cause of the The state must be restored, and the cause of the interruption dealt with, before it is allowed to continue t of ingenuity and hardware are devoted in modern A lot of ingenuity and hardware are devoted in modern processors exactly to ensure that such interruptions do not happen UltraSPARC II – 9 stage pipeline Pentium Pro – 12 stage pipeline entium 4
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This note was uploaded on 01/15/2012 for the course CSC 230 taught by Professor Jasond.corless during the Summer '11 term at University of Victoria.

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W10_17_Pipelining - 17 Introduction to Pipelining CSC CSC...

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