W10_18_IO1_Bus - 18 I/O and Peripherals Part 1: Bus...

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18 I/O and Peripherals Part 1: Bus Structures CSC 230 1
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Bus Basics again: REVIEW Bus Transaction: - a sequence of bus operations - send address + send/receive data memory or to eripherals Î to memory or to peripherals Synchronous: - clock as part of control lines - fixed protocol relative to clock - fast, little hardware - usually only for memory Asynchronous: - not clocked - good for variety of devices - needs handshaking protocol, which means a series of steps to coordinate transfers 2
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Where do we find a “bus”? BUS is at times an overused label Î be careful On the motherboard: System bus Inside a processor: he atapath External I/O: Everything else o peripherals to memory and connections to external I/O busses Î The datapath To peripherals 3
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Microprogramming There is a lot more in the textbook than necessary for this course 1. Read (superficially) for the overall content sections 7.5 in HVZ (5.1 to 5.4 in Murdocca) 2. Example for datapath behaviour given in the lecture notes here with a different (simpler) implementation What is microprogramming? Programming at the level of the control unit in the CPU, the ALU signals, the transfers between registers Î The micro steps which actually implement instructions 4 Microarchitecture design and microprogramming can change without changes needed in the ISA itself
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Look again inside the CPU: Datapath and Control ± Datapath - supports data transfer and processing operations ± Control Unit - Determines the enabling and sequencing of the operations DATAPATH DESIGN: ± A difficult task consisting of: ¾ Choosing number of registers ¾ Choosing number of busses ± Tightly related to the instruction set (register operations) ± Choices impact performance (cycles per instructions) and complexity (number of states, output signals) of controller ± Three choices for datapath bus structures: 1. Point to point ( infeasible in most cases) 5 2. Single bus 3. Multiple bus
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Control signals Internal processor bus/datapath Address lines PC MAR Instruction decoder and control logic Data MDR R Memory bus atapath As seen before for examples in Fetch lines Y IR R0 Constant 4 cessor d – Decode – Execute cycle Add MUX Select ernal pr o Carry-in ALU XOR Sub control ALU lines R n 1 - () A B Int e 6 Z 6
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Datapath Design Example ata bus Address M M P I A A Data bus bus US A R B R C R C C B BUS Architecture 1 Can we do better than this basic structure with one path? a) Consider the operations and their intersections b) IF some operations do not use the same components ever at the same time, the datapath can be subdivided into roups 7 groups
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Datapath Design Example: Change 3 PATH 1 PATH 3 Address bus P C M A R I R A C Data bus M B R A B PATH 2 Part 1: ¾ MAR IR ¾ MAR PC Part 2: ¾ IR MBR ¾ AC MBR LU [B] BR Part 3: ¾ MBR AC ¾ AC MBR C LU ¾ PC IR<13:0> Note that these operations are never done in the ¾ ALU [B] MBR Note that these operations are never done in the ¾ AC ALU Note that these operations are never done in the 10 same state same state same state
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W10_18_IO1_Bus - 18 I/O and Peripherals Part 1: Bus...

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