W11_20_Memory - 20 Memory CSC 230 Department of Computer...

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20 Memory CSC 230 Department of Computer Science University of Victoria
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Performance processor peed everything else in the speed architecture emory speed etc. memory speed transfers between processor and emory memory ast Fast Large Inexpensive difficult to achieve all Memory p 2
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maximum sizes (some items from midterm questions) ± n- it ddress bus Î 2 n ddressable locations n bit address bus 2 addressable locations ± byte-addressable versus word-addressable ± little endian (Intel) versus big endian (PPC) [ARM both] ± implementation is difficult ± block transfers review address ata data addr. strobe lock ontrol emory read/write clock control processor memory 3
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A lot of definitions (1) ± read operation: the transfer of information FROM memory – also “fetch” or “get” rite operation: e transfer of information O ± write operation: the transfer of information TO memory –also “put” ± memory access time: from the beginning to the end of a ead or rite peration read or write operation ± memory cycle time: delay between the start of 2 operations Î (can be a bottleneck) also: a measure of the time required for a read or write operation plus any time required before the memory is ready for the next operation 4
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A lot of definitions (2) ± volatile memory: loses its contents when power turned ff is turned off ± nonvolatile memory: keeps its contents when power is turned off ± capacity: the total amount of information that can be stored in a storage device (e.g. memory) y) ± density: measure of information stored per unit of chip space 5
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A lot of definitions (3) ± random access memory (RAM): memory chip where the actual location has little effect on how long it takes to access information (RAM) ± Read-only memory (ROM): contents are fixed (ROM), burned at manufacturing time and read-only ± ROM Applications: Firmware, Bootstrap memory, Data bles tables ± static memory: semiconductor memory ; the contents remain as long as power applied is applied ± dynamic memory: semiconductor memory for which the contents have to be periodically refreshed, typically every 8-64 ms 6
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The Storage Hierarchy Computer Architecture and Organization by M. Murdocca and V. Heuring © 2007 M. Murdocca and V. Heuring 7
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MAIN FEATURES: Static RAM ± Retain state while power is applied ± Bits stored as on/off switches sually about 6 CMOS transistors per bit ± Usually about 6 CMOS transistors per bit ± No charges (capacitance) to leak ± No refreshing needed when powered ± More complex construction ± Larger per bit FAST XPENSIVE oth in area and manufacturing costs EXPENSIVE Î both in area and manufacturing costs NOT VERY DENSE used for Cache and registers 8
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STATIC RAM CELL word enable READ: sensors for “difference” in voltage between bit and bit enable (sense amplifiers) bit bit transistors Transistor (n): when +5v Î current flows between sides inverter gates when +0v no current flows 9
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Transistor +5 V logical 1) +0 V logical 0) (logical 1) (logical 0) Current flows between sides (between source and sink) No current flow X
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This note was uploaded on 01/15/2012 for the course CSC 230 taught by Professor Jasond.corless during the Summer '11 term at University of Victoria.

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W11_20_Memory - 20 Memory CSC 230 Department of Computer...

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