W11_21_Cache - 21 Cache Organization CSC 230 Department of...

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21 Cache Organization CSC 230 Department of Computer Science University of Victoria
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Cache storage : locality of reference 0% of execution time spent on 10% of code Cache: a safe place for hiding or storing things (Webster’s) 90% of execution time spent on 10% of code Temporal locality when the CPU accesses a piece of information, there is a high probability it will be accessed again soon in time Spatial locality when the CPU accesses a piece of information, there is a high probability that the data in nearby locations will be accessed as well
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Cache : locality of reference Î when data is accessed, transfer an djacent block to cache Î when data is accessed 1 st time, put in cache, ready r next time adjacent block to cache (and/or use a large block size) for next time patial locality emporal locality Spatial locality Temporal locality ± Put ACTIVE segments of program in fast cache memory ± Cache operations are supported by hardware control
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Cache : placement and speed Computer Architecture and Organization by M. Murdocca and V. Heuring © 2007 M. Murdocca and V. Heuring
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The cache consists of a number of cache lines Each cache line consists of two parts a block of memory an address tag which pecifies the starting (copied from main memory) specifies the starting memory location of the cache entry cache hit: when data is found in the cache ache iss: hen data is not found in the cache cache miss: when data is not found in the cache (next go to memory) ache ll: eed to decide how to create space cache full: need to decide how to create space Î replacement
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A few more definitions about cache iss rate e fraction of memory accesses not found in a Miss rate – the fraction of memory accesses not found in a level of the memory hierarchy (e.g. L1 cache miss because data is in RAM) Hit time – the time required to access a level of the memory hierarchy, including the time needed to determine whether the access is a hit or a miss Miss penalty – the time required to fetch a block into a level of the memory hierarchy from the wer level cluding: lower level, including: the time to access the block, transmit it from one level to the other, sert in the level that experienced the insert it in the level that experienced the miss
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How the Cache and the CPU operate together 1. CPU requests contents of memory location 2. Cache is checked first for this data ( hardware-supported search ) 3. [3A] If present, get data from cache (fast) [3B.1] If not present, issue a READ for the required block from main memory to cache [3B.2] Then copy from cache to CPU ache includes tags to identify which block of main 4. Cache includes tags to identify which block of main memory is in each cache slot
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Cache design issues In detail here 9 Size apping Function 9 Mapping Function 9 Replacement Algorithm 9 Write Policy efinitions only this course 9 Block Size 9 Number of Caches Definitions only in this course
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Write Policy ± Write-through protocol + cache and memory are updated at the same time imple + simple +
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W11_21_Cache - 21 Cache Organization CSC 230 Department of...

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