W12_22_CacheExamples1

W12_22_CacheExamples1 - 20a Cache Examples Part 1 CSC 230...

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Unformatted text preview: 20a Cache Examples Part 1 CSC 230 Department of Computer Science University of Victoria Problem 5.7 (from textbook) computer uses a small direct apped cache between the main memory A computer uses a small direct-mapped cache between the main memory and the processor. The cache has four 16-bit words , and each word has an associated 13-bit tag, as shown in the figure below. When a miss occurs uring a read operation, the requested word is read from the main memory during a read operation, the requested word is read from the main memory and sent to the processor. At the same time, it is copied into the cache, and its block number is stored in the associated tag. 13 bits 16 bits Tag Content address 0 ddress 2 address 2 address 4 address 6 Consider the following loop in a program where all instructions and perands are 16 bits long and the code starts at address 2EC operands are 16 bits long and the code starts at address 02EC : LOOP: ADD (R1)+,R0 02EC DECR R2 02EE BNE LOOP 02F0 Assume that, before this loop is entered, registers R0, R1 and R2 contain: R0 = 0, R1 = 054E, R2 = 3. Also assume that main memory contains the data as shown below: 03C 54E Show the contents of the cache at the end of each pass through the loop. A03C 054E 05D9 0550 0D7 552 10D7 0552 DD 2EC ADD 02EC DECR 02EE NE 2F0 LOOP: ADD (R1)+,R0 02EC DECR R2 02EE BNE LOOP 02F0 BNE 02F0 anslated to ARM code . . . . OOP: DR 3,[R1],#4 translated to ARM code A03C 054E 5D9 550 LOOP: LDR R3,[R1],#4 ADD R0,R0,R3 SUBS R2,R2,#1 BNE LOOP 05D9 0550 10D7 0552 Example will remain in language as the book for consistency of the answers LOOP: ADD (R1)+,R0 02EC = 0000 0010 1110 1100 4 DECR R2 02EE = 0000 0010 1110 1110 6 BNE LOOP 02F0 = 0000 0010 1111 0000 3 bits = which lock cache tag block in cache A03C 054E = 0000 0101 0100 1110 6 05D9 0550 = 0000 0101 0101 0000 10D7 0552 = 0000 0101 0101 0010 2 this tells us the cache block number where each instruction ill be stored this tells us the cache block number where each data will be stored will be stored LOOP: ADD (R1)+,R0 02EC = 0000 0010 1110 1100 4 DECR R2 02EE = 0000 0010 1110 1110 6 BNE LOOP 02F0 = 0000 0010 1111 0000 A03C 054E = 0000 0101 0100 1110 6 R0 = 0 05D9 0550 = 0000 0101 0101 0000 10D7 0552 = 0000 0101 0101 0010 2 R1 = 054E R2 = 3 13 bits 16 bits Tag Content address 0 address 2 address 4 address 6 LOOP: ADD (R1)+,R0 02EC = 0000 0010 1110 1100 4 DECR R2 02EE = 0000 0010 1110 1110 6 BNE LOOP 02F0 = 0000 0010 1111 0000 R0 = 0 A03C 054E = 0000 0101 0100 1110 6 R1 = 054E R2 = 3 05D9 0550 = 0000 0101 0101 0000 10D7 0552 = 0000 0101 0101 0010 2 13 bits 16 bits Tag Content Fetch ADD (1 M) address 0 address 2 address 4 ADD address 6 LOOP: ADD (R1)+,R0 02EC = 0000 0010 1110 1100 4 DECR R2 02EE = 0000 0010 1110 1110 6 BNE LOOP 02F0 = 0000 0010 1111 0000 R0 = 0 A03C 054E = 0000 0101 0100 1110 6 R1 = 054E R2 = 3 05D9 0550 = 0000 0101 0101 0000 10D7 0552 = 0000 0101 0101 0010 2 13 bits...
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W12_22_CacheExamples1 - 20a Cache Examples Part 1 CSC 230...

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