W13_24_Processors - 24 Processors CSC 230 Department of...

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24 Processors CSC 230 Department of Computer Science University of Victoria
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Most notably, 1975, ost otab y, 9 5, Moore altered his projection to a doubling every two ears . [Source: y [ Wikipedia entry for “Moore’s Law”.] Source: Wikipedia entry for “Transistor count”
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INTEL ARCHITECTURE [1969] 4004 8080 8085 IA really starts with the 8086 8088 [1971] 4004 4 bit registers - 4 bit external data bus - 12 bit ddressing - 40kHz addressing 740kHz [1974] 8080 8 bit registers - 8 bit external data bus - 16 bit addressing - 2MHz [1978] 8086 16 bit registers - 16 bit ext. data bus - 20 bit addressing - 4.77MHz to 10MHz rograms from 1978 still execute on the latest Î Programs from 1978 still execute on the latest members of the IA family Î downward compatibility
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INTEL 80286 1982 ¾ 32 bit registers for computation and addressing ¾ MMU added, giving paging with a fixed 4K page Î VM ¾ 6 parallel 'stages': ± bus interface unit ± code prefetch unit struction ecode ± instruction decode unit ± execution unit ± segment unit ± paging unit 1.5μm silicon gate CMOS 1 polysilicon layer and 2 metal 134,000 transistors to 12 MHz clock speed layers 6 to 12 MHz clock speed 68.7mm 2 die size
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INTEL 80386 DX - 1985 first 32 bit processor ¾ 5 pipelined stages ± each stage can work on one instruction per clock cycle ¾ 8K on-chip L1 cache was added ¾ Instructions were added to provide L2 (off-chip) ache support and 1.5μm silicon gate CMOS 10 mask layers 275,000 transistors cache support and multiprocessing 16 to 33MHz clock 104mm2 die size
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INTEL 80486 - 1989 first on-chip FP unit 1.0μm silicon gate CMOS 2 mask layers 12 mask layers 1.2 million transistors 5 to 50MHz clock 25 to 50MHz clock 163mm 2 die size
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INTEL PENTIUM 1993 0.8μm silicon gate BiCMOS 18 mask layers 1 million transistors 3.1 million transistors 60 to 66 MHz clock 264mm 2 die size ¾ second execution pipeline for superscalar performance K 1 - ache and K L1 ¾ 8K L1 I cache and 8K L1 D-cache ¾ Branch prediction hardware ¾ 32 bit registers, but 128 and 256 bit internal data paths, external data bus is 64 bits ¾ two processor support
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Main Pentium Features Multiple Branch Prediction : ± Predicts flow of the program through several branches. ± 0% or greater accuracy for finding next instruction. 90% or greater accuracy for finding next instruction. Data Flow Analysis : ± Analyzes and schedules instructions to be executed in an optimal sequence, independent of the original program order. Speculative Execution : p ± Looks ahead of the program counter and executes instructions that are likely to be needed.
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This note was uploaded on 01/15/2012 for the course CSC 230 taught by Professor Jasond.corless during the Summer '11 term at University of Victoria.

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W13_24_Processors - 24 Processors CSC 230 Department of...

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