Assn8_soln - CDA 3101 Assignment 8 Due in class on Friday,...

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Unformatted text preview: CDA 3101 Assignment 8 Due in class on Friday, Dec. 8 Turn hardcopy in class, stapled, with your name and “CDA 3101 Assignment 8”clearly written on it. NO LATE SUBMISSIONS WILL BE ACCEPTED FOR THIS HOMEWORK. 1. a. (3 points) Problem 4.12.1a from the textbook(4th edition). Pipelined: 500ps Single‐Cycle: 1650ps b. (3 points) Problem 4.12.2a from the textbook(4th edition). Pipelined: 2500ps Single‐Cycle: 1650ps c. (3 points) Problem 4.12.3a from the textbook(4th edition) MEM, new cycle time = 400 ps d. (2 points) Problem 4.12.6b from the textbook(4th edition) Multi‐cycle/ pipeline = 0.3*5 + 0.7*4 = 4.3 Single‐cycle/ pipeline = 800/200 =4.00 2. a. (2 points) Problem 4.13.2b from the textbook(4th edition). b. (2 points) Problem 4.13.3b from the textbook(4th edition). c. (2 points) Problem 4.13.4b from the textbook(4th edition) No forwarding: 9*200ps = 1800ps With forwarding: 8*250ps = 2000ps Speedup = 1800/2000 = 0.9 d. (2 points) Problem 4.13.5b from the textbook(4th edition) e. (2 points) Problem 4.13.6b from the textbook(4th edition) No forwarding: 9*200ps = 1800ps With only ALU‐ALU forwarding: 9*220ps = 1980ps Speedup = 1800/1980 = 0.91 3. (10 points) Consider the following code being executed on the pipelined datapath/control shown on the last page. Assume that we are using the “nullify if taken” branch strategy discussed in class and in the book. Also, assume that $t3 = $t6 when beq $t3, $t6, label is executed. a. Determine where the hazards occur and what type of hazard each is. If an instruction is not executed, write “NOT EXECUTED” next to it. add $t1, $t1, $t2 # No hazard sub $t1, $t1, $t3 # Data hazard occurs because $t1 is used as a source here and #$t1 is the #destination register in the previous instruction. and $t2, $t0, $t1 # Data hazard occurs because $t1 is used as a source here and #$t1 is the #destination register in the previous instruction. lw $t0, 0($t1) # Data hazard occurs because $t1 is used as a source here add $t3, $t0, $t1 # Data hazard occurs because $t0 (written by LW) #instruction is used as source in this instruction beq $t3, $t6, label # Control hazard occurs since we won’t know for 3 more # cycles which direction to go...we just keep going at the #moment assuming the branch is taken. or $t1, $t0, $t2 # No hazards occur since $t0 was last produced by the lw # instruction, which is farther than 2 cycles away nor $t3, $t2, $t4 # No hazards occur with this instruction either since $t2 was #last produced by the and instruction farther than 2 cycles #away. add $s0, $s1, $s2 # No Hazard add $s1, $s2, $s3 # Not Fetched label: lw $t0, 4($t1) # No hazards sw $t0, 8($t1) # Data hazard because of $t0 produced by LW instruction is #used as source in this instruction b. (14 points) Indicate in the chart below what stage each instruction is in at what cycle. Show occurrence of forwarding by drawing an arrow from where the value is produced to where the value is used, and show occurrence of stalls by writing “STALL” in that clock cycle. Also indicate if any instruction is flushed (i.e., cancelled) by writing “FL” in the appropriate clock cycle. Make sure you fill in the instructions in the first column as they would execute. The table below may have more/less clock cycles than you need. Also state from the filled out chart HOW MANY CYCLES this code took to execute. Instru Add $t1, $t1, $t2 cc1 F cc2 D cc3 E cc4 M cc5 W cc6 cc7 cc8 cc9 cc10 cc11 cc12 cc13 cc14 cc15 cc16 Sub $t1, $t1, $t3 F D E M W And $t2, $t0, $t1 F D E M W F D E M W F D stall E M W F stall D E M W stall F D E FL Lw $t0, 0($t1) Add $t3, $t0, $t1 Beq $t3, $t6, label Or $t1, $t0, $t2 Nor $t3, $t2, $t4 D FL Add $s0, $s1, $s2 F FL Add $s1, $s2, $s3 Not Feched Lw $t0, 4($t1) F D E M W Sw $t0, 8($t1) F D E M In total 16 cycles are required F W c. (5 points) Redo part (b) now assuming that the branch decision is made in the decode stage instead of the MEM stage? Instru Add $t1, $t1, $t2 cc1 F cc2 D cc3 E cc4 M cc5 W cc6 cc7 cc8 cc9 cc10 W M W Sub $t1, $t1, $t3 F D E M W And $t2, $t0, $t1 F D E M F D E M W F D stall E Lw $t0, 0($t1) Add $t3, $t0, $t1 cc11 cc12 cc13 cc14 cc15 cc16 Beq $t3, $t6, label F stall stall D E M W Or $t1, $t0, $t2 stall stall F FL Nor $t3, $t2, $t4 Not Feched Add $s0, $s1, $s2 Add $s1, $s2, $s3 Not Feched Lw $t0, 4($t1) F D E M W Sw $t0, 8($t1) F D E M W In total 15 cycles are needed. Not Feched ...
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