24AA256,24LC256,24FC256-EEProm

24AA256,24LC256,24FC256-EEProm - M 24AA256/24LC256/24FC256...

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Unformatted text preview: M 24AA256/24LC256/24FC256 256K I2C™ CMOS Serial EEPROM Features Description • Low power CMOS technology - Maximum write current 3 mA at 5.5 V - Maximum read current 400 µA at 5.5 V - Standby current 100 nA typical at 5.5 V • 2-wire serial interface bus, I2C compatible • Cascadable for up to eight devices • Self-timed ERASE/WRITE cycle • 64-byte page-write mode available • 5 ms max write-cycle time • Hardware write protect for entire array • Output slope control to eliminate ground bounce • Schmitt trigger inputs for noise suppression • 1,000,000 erase/write cycles • Electrostatic discharge protection > 4000 V • Data retention > 200 years • 8-pin PDIP, SOIC, TSSOP, MSOP, and DFN packages • 14-lead TSSOP package • Temperature ranges: - Industrial (I): -40 °C to +85°C - Automotive (E): -40 °C to +125°C The Microchip Technology Inc. 24AA256/24LC256/ 24FC256 (24XX256*) is a 32K x 8 (256 Kbit) Serial Electrically Erasable PROM, capable of operation across a broad voltage range (1.8 V to 5.5 V). It has been developed for advanced, low power applications such as personal communications or data acquisition. This device also has a page-write capability of up to 64 bytes of data. This device is capable of both random and sequential reads up to the 256K boundary. Functional address lines allow up to eight devices on the same bus, for up to 2 Mbit address space. This device is available in the standard 8-pin plastic DIP, SOIC, TSSOP, MSOP, DFN and 14-lead TSSOP packages. Block Diagram A0 A1 A2WP I/O CONTROL LOGIC MEMORY CONTROL LOGIC HV GENERATOR EEPROM ARRAY XDEC PAGE LATCHES I/O SCL Device Selection Table YDEC SDA Part Number VCC Range Max. Clock Frequency 400 kHz Temp. Ranges (1) VCC I 24AA256 1.8-5.5 V 24LC256 2.5-5.5 V 400 kHz I, E 24FC256 2.5-5.5 V 1 MHz SENSE AMP R/W CONTROL VSS I Note 1: 100 kHz for VCC < 2.5 V. Package Types PDIP/SOIC A0 5 SCL SDA A1 A2 VSS 1 2 3 4 8 7 6 5 VCC WP SCL SDA A0 A1 NC NC NC A2 VSS 1 2 3 4 5 6 7 DFN 14 13 12 11 10 9 8 VCC WP NC NC NC SCL SDA A0 1 A1 2 A2 3 VSS 4 8 VCC 24XX256 4 6 WP A0 24XX256 VSS 3 7 VCC 24XX256 A2 2 24XX256 A1 8 1 TSSOP TSSOP/MSOP * 7 WP 6 SCL 5 SDA * Pins A0 and A1 are no connects for the MSOP package only. *24XX256 is used in this document as a generic part number for the 24AA256/24LC256/24FC256 devices. 2002 Microchip Technology Inc. Preliminary DS21203J-page 1 24AA256/24LC256/24FC256 1.0 ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings† VCC ............................................................................................................................................................................6.5 V All inputs and outputs w.r.t. VSS ....................................................................................................... -0.6 V to VCC +1.0 V Storage temperature ...............................................................................................................................-65°C to +150°C Ambient temp. with power applied ..........................................................................................................-65°C to +125°C ESD protection on all pins ......................................................................................................................................................≥ 4 kV † NOTICE: Stresses above those listed under “Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. 1.1 24AA256/24LC256/24FC256 DC Electrical Specifications Electrical Characteristics: Industrial (I): VCC = +1.8 V to 5.5 V Automotive (E): VCC = +2.5 V to 5.5 V DC Specifications Param. No. Sym D1 — Characteristic Min Max Units A0, A1, A2, SCL, SDA and WP pins: — — — TAMB = -40°C to +85°C TAMB = -40°C to +125°C Conditions — D2 VIH High level input voltage 0.7 VCC — V — D3 VIL Low level input voltage — 0.3 VCC 0.2 V CC V V VCC ≥ 2.5 V VCC < 2.5 V D4 VHYS 0.05 VCC — V VCC ≥ 2.5 V (Note) D5 VOL Low level output voltage — 0.40 V IOL = 3.0 ma @ VCC = 4.5 V IOL = 2.1 ma @ VCC = 2.5 V D6 ILI Input leakage current — ±10 µA VIN = VSS or VCC, WP = VSS VIN = VSS or VCC, WP = VCC D7 ILO Output leakage current — ±10 µA VOUT = VSS or VCC D8 CIN, COUT Pin capacitance (all inputs/outputs) — 10 pF VCC = 5.0 V (Note) TAMB = 25°C, fC = 1 MHz ICC Read Operating current — 400 µA VCC = 5.5 V, SCL = 400 kHz ICC Write — 3 mA VCC = 5.5 V — 1 µA TAMB = -40°C to +85°C SCL = SDA = VCC = 5.5 V A0, A1, A2, WP = VSS — 5 µA TAMB = -40°C to +125°C SCL = SDA = VCC = 5.5 V A0, A1, A2, WP = VSS D9 D10 Note: ICCS Hysteresis of Schmitt Trigger inputs (SDA, SCL pins) Standby current This parameter is periodically sampled and not 100% tested. DS21203J-page 2 Preliminary 2002 Microchip Technology Inc. 24AA256/24LC256/24FC256 1.2 24AA256/24LC256/24FC256 AC Electrical Specifications Electrical Characteristics: Industrial (I): VCC = +1.8 V to 5.5 V Automotive (E): VCC = +2.5 V to 5.5 V AC Specifications Param. No. Sym 1 FCLK 2 Characteristic TAMB = -40°C to +85°C TAMB = -40°C to +125°C Min Max Units Conditions Clock frequency — — — 100 400 1000 kHz 1.8 V ≤ VCC < 2.5 V 2.5 V ≤ VCC ≤ 5.5 V 2.5 V ≤ VCC ≤ 5.5 V 24FC256 THIGH Clock high time 4000 600 500 — — — ns 1.8 V ≤ VCC < 2.5 V 2.5 V ≤ VCC ≤ 5.5 V 2.5 V ≤ VCC ≤ 5.5 V 24FC256 3 TLOW Clock low time 4700 1300 500 — — — ns 1.8 V ≤ VCC < 2.5 V 2.5 V ≤ VCC ≤ 5.5 V 2.5 V ≤ VCC ≤ 5.5 V 24FC256 4 TR SDA and SCL rise time (Note 1) — — — 1000 300 300 ns 1.8 V ≤ VCC < 2.5 V 2.5 V ≤ VCC ≤ 5.5 V 2.5 V ≤ VCC ≤ 5.5 V 24FC256 5 TF SDA and SCL fall time (Note 1) — — 300 100 ns All except, 24FC256 2.5 V ≤ VCC ≤ 5.5 V 24FC256 6 THD :STA START condition hold time 4000 600 250 — — — ns 1.8 V ≤ VCC < 2.5 V 2.5 V ≤ VCC ≤ 5.5 V 2.5 V ≤ VCC ≤ 5.5 V 24FC256 7 TSU:STA START condition setup time 4700 600 250 — — — ns 1.8 V ≤ VCC < 2.5 V 2.5 V ≤ VCC ≤ 5.5 V 2.5 V ≤ VCC ≤ 5.5 V 24FC256 8 THD:DAT Data input hold time 9 TSU:DAT Data input setup time 0 — ns (Note 2) 250 100 100 — — — ns 1.8 V ≤ VCC < 2.5 V 2.5 V ≤ VCC ≤ 5.5 V 2.5 V ≤ VCC ≤ 5.5 V 24FC256 10 TSU :STO STOP condition setup time 4000 600 250 — — — ns 1.8 V ≤ VCC < 2.5 V 2.5 V ≤ VCC ≤ 5.5 V 2.5 V ≤ VCC ≤ 5.5 V 24FC256 11 TSU:WP WP setup time 4000 600 600 — — — ns 1.8 V ≤ VCC < 2.5 V 2.5 V ≤ VCC ≤ 5.5 V 2.5 V ≤ VCC ≤ 5.5 V 24FC256 12 THD:WP WP hold time 4700 1300 1300 — — — ns 1.8 V ≤ VCC < 2.5 V 2.5 V ≤ VCC ≤ 5.5 V 2.5 V ≤ VCC ≤ 5.5 V 24FC256 13 TAA Output valid from clock (Note 2) — — — 3500 900 400 ns 1.8 V ≤ VCC < 2.5 V 2.5 V ≤ VCC ≤ 5.5 V 2.5 V ≤ VCC ≤ 5.5 V 24FC256 14 TBUF Bus free time: Time the bus must be free before a new transmission can start 4700 1300 500 — — — ns 1.8 V ≤ VCC < 2.5 V 2.5 V ≤ VCC ≤ 5.5 V 2.5 V ≤ VCC ≤ 5.5 V 24FC256 15 TOF Output fall time from VIH minimum to VIL maximum CB ≤ 100 pF 10 + 0.1CB 250 250 ns All except, 24FC256 (Note 1) 24FC256 (Note 1) 16 TSP Input filter spike suppression (SDA and SCL pins) — 50 ns All except, 24FC256 (Notes 1 and 3) 17 TWC Write cycle time (byte or page) — 18 — Note Endurance — 5 ms 1,000,000 — cycles 25°C (Note 4) 1: Not 100% tested. CB = total capacitance of one bus line in pF. 2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region (minimum 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions. 3: The combined TSP a nd VHYS specifications are due to new Schmitt trigger inputs, which provide improved noise spike suppression. This eliminates the need for a TI specification for standard operation. 4: This parameter is not tested but ensured by characterization. For endurance estimates in a specific application, please consult the Total Endurance Model, which can be obtained on Microchip’s website: www.microchip.com. 2002 Microchip Technology Inc. Preliminary DS21203J-page 3 24AA256/24LC256/24FC256 FIGURE 1-1: BUS TIMING DATA 5 SCL 7 SDA IN 3 4 D4 2 8 10 9 6 16 14 13 SDA OUT WP DS21203J-page 4 (protected) (unprotected) Preliminary 11 12 2002 Microchip Technology Inc. 24AA256/24LC256/24FC256 2.0 PIN DESCRIPTIONS The descriptions of the pins are listed in Table 2-1. TABLE 2-1: PIN FUNCTION TABLE Name 8-pin PDIP 8-pin SOIC 8-pin TSSOP 14-pin TSSOP 8-pin MSOP 8-pin DFN A0 1 1 1 1 — 1 User Configurable Chip Select A1 2 2 2 2 — 2 User Configurable Chip Select (NC) — — — 3, 4, 5 1,2 — Not Connected Function A2 3 3 6 3 3 User Configurable Chip Select 4 4 4 7 4 4 Ground SDA 5 5 5 8 5 5 Serial Data SCL 6 6 6 9 6 6 Serial Clock (NC) — — — 10, 11, 12 — — Not Connected WP 7 7 7 13 7 7 Write Protect Input VCC 2.1 3 VSS 8 8 8 14 8 8 +1.8 V to 5.5 V (24AA256) +2.5 V to 5.5 V (24LC256) +2.5 V to 5.5 V (24FC256) A0, A1, A2 Chip Address Inputs 2.3 Serial Clock (SCL) The A0, A1 and A2 inputs are used by the 24XX256 for multiple device operations. The levels on these inputs are compared with the corresponding bits in the slave address. The chip is selected if the compare is true. This input is used to synchronize the data transfer to and from the device. For the MSOP package only, pins A0 and A1 are not connected. This pin can be connected to either VSS, VCC or left floating. Internal pull-down circuitry on this pin will keep the device in the unprotected state if left floating. If tied to VSS or left floating, normal memory operation is enabled (read/write the entire memory 0000-7FFF). Up to eight devices (two for the MSOP package) may be connected to the same bus by using different chip select bit combinations. If these pins are left unconnected, the inputs will be pulled down internally to VSS. If they are tied to VCC or driven high, the internal pulldown circuitry is disabled. In most applications, the chip address inputs A0, A1 and A2 are hard-wired to logic ‘0’ or logic ‘1’. For applications in which these pins are controlled by a microcontroller or other programmable device, the chip address pins must be driven to logic ‘0’ or logic ‘1’ before normal device operation can proceed. 2.2 Serial Data (SDA) This is a bi-directional pin used to transfer addresses and data into and out of the device. It is an open drain terminal. Therefore, the SDA bus requires a pull-up resistor to VCC (typical 10 kΩ for 100 kHz, 2 kΩ for 400 kHz and 1 MHz). 2.4 Write Protect (WP) If tied to VCC, WRITE operations are inhibited. Read operations are not affected. 3.0 FUNCTIONAL DESCRIPTION The 24XX256 supports a bi-directional 2-wire bus and data transmission protocol. A device that sends data onto the bus is defined as a transmitter and a device receiving data as a receiver. The bus must be controlled by a master device which generates the serial clock (SCL), controls the bus access, and generates the START and STOP conditions while the 24XX256 works as a slave. Both master and slave can operate as a transmitter or receiver, but the master device determines which mode is activated. For normal data transfer SDA is allowed to change only during SCL low. Changes during SCL high are reserved for indicating the START and STOP conditions. 2002 Microchip Technology Inc. Preliminary DS21203J-page 5 24AA256/24LC256/24FC256 4.0 BUS CHARACTERISTICS The data on the line must be changed during the LOW period of the clock signal. There is one bit of data per clock pulse. The following bus protocol has been defined: • Data transfer may be initiated only when the bus is not busy. • During data transfer, the data line must remain stable whenever the clock line is HIGH. Changes in the data line while the clock line is HIGH will be interpreted as a START or STOP condition. Each data transfer is initiated with a START condition and terminated with a STOP condition. The number of the data bytes transferred between the START and STOP conditions is determined by the master device. 4.5 Each receiving device, when addressed, is obliged to generate an acknowledge signal after the reception of each byte. The master device must generate an extra clock pulse which is associated with this acknowledge bit. Accordingly, the following bus conditions have been defined (Figure 4-1). 4.1 Bus not Busy (A) Both data and clock lines remain HIGH. 4.2 Note: Start Data Transfer (B) A HIGH to LOW transition of the SDA line while the clock (SCL) is HIGH determines a START condition. All commands must be preceded by a START condition. 4.3 A LOW to HIGH transition of the SDA line while the clock (SCL) is HIGH determines a STOP condition. All operations must end with a STOP condition. Data Valid (D) The state of the data line represents valid data when, after a START condition, the data line is stable for the duration of the HIGH period of the clock signal. FIGURE 4-1: (A) The 24XX256 does not generate any acknowledge bits if an internal programming cycle is in progress. A device that acknowledges must pull down the SDA line during the acknowledge clock pulse in such a way that the SDA line is stable LOW during the HIGH period of the acknowledge related clock pulse. Of course, setup and hold times must be taken into account. During reads, a master must signal an end of data to the slave by NOT generating an acknowledge bit on the last byte that has been clocked out of the slave. In this case, the slave (24XX256) will leave the data line HIGH to enable the master to generate the STOP condition. Stop Data Transfer (C) 4.4 Acknowledge DATA TRANSFER SEQUENCE ON THE SERIAL BUS (B) (D) (D) (C) (A) SCL SDA START CONDITION FIGURE 4-2: ADDRESS OR DATA ACKNOWLEDGE ALLOWED VALID TO CHANGE STOP CONDITION ACKNOWLEDGE TIMING Acknowledge Bit 1 SCL SDA 2 3 4 5 6 7 8 Data from transmitter 1 2 3 Data from transmitter Transmitter must release the SDA line at this point, allowing the Receiver to pull the SDA line low to acknowledge the previous eight bits of data. DS21203J-page 6 9 Preliminary Receiver must release the SDA line at this point so the Transmitter can continue sending data. 2002 Microchip Technology Inc. 24AA256/24LC256/24FC256 5.0 DEVICE ADDRESSING FIGURE 5-1: A control byte is the first byte received following the start condition from the master device (Figure 5-1). The control byte consists of a 4-bit control code. For the 24XX256, this is set as 1010 binary for read and write operations. The next three bits of the control byte are the chip select bits (A2, A1, A0). The chip select bits allow the use of up to eight 24XX256 devices on the same bus and are used to select which device is accessed. The chip select bits in the control byte must correspond to the logic levels on the corresponding A2, A1 and A0 pins for the device to respond. These bits are, in effect, the three most significant bits of the word address. For the MSOP package, the A0 and A1 pins are not connected. During device addressing, the A0 and A1 chip select bits (Figures 5-1 and 5-2) should be set to ‘0’. Only two 24XX256 MSOP packages can be connected to the same bus. The last bit of the control byte defines the operation to be performed. When set to a one, a read operation is selected. When set to a zero, a write operation is selected. The next two bytes received define the address of the first data byte (Figure 5-2). Because only A14…A0 are used, the upper address bits are a don’t care. The upper address bits are transferred first, followed by the less significant bits. Following the start condition, the 24XX256 monitors the SDA bus checking the device type identifier being transmitted. Upon receiving a 1010 code and appropriate device select bits, the slave device outputs an acknowledge signal on the SDA line. Depending on the state of the R/W bit, the 24XX256 will select a read or write operation. FIGURE 5-2: 0 1 CONTROL CODE Read/Write Bit Chip Select Bits Control Code S 1 0 1 0 A2 A1 A0 R/W ACK Slave Address Start Bit 5.1 Acknowledge Bit Contiguous Addressing Across Multiple Devices The chip select bits A2, A1, A0 can be used to expand the contiguous address space for up to 2 Mbit by adding up to eight 24XX256s on the same bus. In this case, software can use A0 of the control byte as address bit A15; A1 as address bit A16; and A2 as address bit A17. It is not possible to sequentially read across device boundaries. For the MSOP package, up to two 24XX256 devices can be added for up to 512 Kbit of address space. In this case, software can use A2 of the control byte as address bit A17. Bits A0 (A15) and A1 (A16) of the control byte must always be set to a logic ‘0’ for the MSOP. ADDRESS SEQUENCE BIT ASSIGNMENTS CONTROL BYTE 1 CONTROL BYTE FORMAT 0 A 2 A 1 ADDRESS HIGH BYTE A 0 R/W X AAAAA 14 13 12 11 10 A 9 CHIP SELECT BITS 2002 Microchip Technology Inc. ADDRESS LOW BYTE A 8 A 7 • • • • • • A 0 X = Don’t Care Bit Preliminary DS21203J-page 7 24AA256/24LC256/24FC256 6.0 WRITE OPERATIONS 6.1 Byte Write transmit more than 64 bytes prior to generating the stop condition, the address counter will roll over and the previously received data will be overwritten. As with the byte write operation, once the stop condition is received, an internal write cycle will begin (Figure 6-2). If an attempt is made to write to the array with the WP pin held high, the device will acknowledge the command but no write cycle will occur, no data will be written and the device will immediately accept a new command. Following the start condition from the master, the control code (four bits), the chip select (three bits) and the R/W bit (which is a logic low) are clocked onto the bus by the master transmitter. This indicates to the addressed slave receiver that the address high byte will follow after it has generated an acknowledge bit during the ninth clock cycle. Therefore, the next byte transmitted by the master is the high-order byte of the word address and will be written into the address pointer of the 24XX256. The next byte is the least significant address byte. After receiving another acknowledge signal from the 24XX256, the master device will transmit the data word to be written into the addressed memory location. The 24XX256 acknowledges again and the master generates a stop condition. This initiates the internal write cycle and during this time, the 24XX256 will not generate acknowledge signals (Figure 6-1). If an attempt is made to write to the array with the WP pin held high, the device will acknowledge the command but no write cycle will occur, no data will be written, and the device will immediately accept a new command. After a byte write command, the internal address counter will point to the address location following the one that was just written. 6.2 6.3 Write Protection The WP pin allows the user to write-protect the entire array (0000-7FFF) when the pin is tied to VCC. If tied to VSS or left floating, the write protection is disabled. The WP pin is sampled at the STOP bit for every write command (Figure 1-1). Toggling the WP pin after the STOP bit will have no effect on the execution of the write cycle. Note: Page write operations are limited to writing bytes within a single physical page, regardless of the number of bytes actually being written. Physical page boundaries start at addresses that are integer multiples of the page buffer size (or ‘page size’) and end at addresses that are integer multiples of [page size - 1]. If a page write command attempts to write across a physical page boundary, the result is that the data wraps around to the beginning of the current page (overwriting data previously stored there), instead of being written to the next page, as might be expected. It is, therefore, necessary for the application software to prevent page write operations that would attempt to cross a page boundary. Page Write The write control byte, word address and the first data byte are transmitted to the 24XX256 in much the same way as in a byte write. The exception is that instead of generating a stop condition, the master transmits up to 63 additional bytes, which are temporarily stored in the on-chip page buffer and will be written into memory once the master has transmitted a stop condition. Upon receipt of each word, the six lower address pointer bits are internally incremented by one. If the master should FIGURE 6-1: BYTE WRITE BUS ACTIVITY MASTER S T A R T CONTROL BYTE S1 0 1 0 AAA 0 210 SDA LINE X = don’t care bit BUS ACTIVITY MASTER SDA LINE AAA S10 1 0 21 00 X = don’t care bit DS21203J-page 8 S T O P DATA P A C K A C K A C K PAGE WRITE S T A R T BUS ACTIVITY ADDRESS LOW BYTE X A C K BUS ACTIVITY FIGURE 6-2: ADDRESS HIGH BYTE CONTROL BYTE ADDRESS HIGH BYTE ADDRESS LOW BYTE DATA BYTE 0 S T O P DATA BYTE 63 X A C K P A C K Preliminary A C K A C K A C K 2002 Microchip Technology Inc. 24AA256/24LC256/24FC256 7.0 ACKNOWLEDGE POLLING FIGURE 7-1: Since the device will not acknowledge during a write cycle, this can be used to determine when the cycle is complete (This feature can be used to maximize bus throughput.) Once the stop condition for a write command has been issued from the master, the device initiates the internally timed write cycle. ACK polling can be initiated immediately. This involves the master sending a start condition, followed by the control byte for a write command (R/W = 0). If the device is still busy with the write cycle, then no ACK will be returned. If no ACK is returned, the start bit and control byte must be resent. If the cycle is complete, then the device will return the ACK and the master can then proceed with the next read or write command. See Figure 7-1 for flow diagram. ACKNOWLEDGE POLLING FLOW Send Write Command Send Stop Condition to Initiate Write Cycle Send Start Send Control Byte with R/W = 0 Did Device Acknowledge (ACK = 0)? NO YES Next Operation 2002 Microchip Technology Inc. Preliminary DS21203J-page 9 24AA256/24LC256/24FC256 8.0 READ OPERATION 8.2 Random read operations allow the master to access any memory location in a random manner. To perform this type of read operation, the word address must first be set. This is done by sending the word address to the 24XX256 as part of a write operation (R/W bit set to ‘0’). Once the word address is sent, the master generates a start condition following the acknowledge. This terminates the write operation, but not before the internal address pointer is set. The master then issues the control byte again but with the R/W bit set to a one. The 24XX256 will then issue an acknowledge and transmit the 8-bit data word. The master will not acknowledge the transfer, though it does generate a stop condition, which causes the 24XX256 to discontinue transmission (Figure 8-2). After a random read command, the internal address counter will point to the address location following the one that was just read. Read operations are initiated in much the same way as write operations, with the exception that the R/W bit of the control byte is set to ‘1’. There are three basic types of read operations: current address read, random read and sequential read. 8.1 Current Address Read The 24XX256 contains an address counter that maintains the address of the last word accessed, internally incremented by ‘1’. Therefore, if the previous read access was to address n (n is any legal address), the next current address read operation would access data from address n + 1. Upon receipt of the control byte with R/W bit set to ‘1’, the 24XX256 issues an acknowledge and transmits the 8-bit data word. The master will not acknowledge the transfer but does generate a stop condition and the 24XX256 discontinues transmission (Figure 8-1). FIGURE 8-1: 8.3 S T A R T SDA LINE S 10 10 AAA1 210 CONTROL BYTE FIGURE 8-2: BUS ACTIVITY MASTER SDA LINE P A C K BUS ACTIVITY S T O P DATA BYTE Sequential Read Sequential reads are initiated in the same way as a random read except that after the 24XX256 transmits the first data byte, the master issues an acknowledge as opposed to the stop condition used in a random read. This acknowledge directs the 24XX256 to transmit the next sequentially addressed 8-bit word (Figure 8-3). Following the final byte transmitted to the master, the master will NOT generate an acknowledge but will generate a stop condition. To provide sequential reads, the 24XX256 contains an internal address pointer which is incremented by one at the completion of each operation. This address pointer allows the entire memory contents to be serially read during one operation. The internal address pointer will automatically roll over from address 7FFF to address 0000 if the master acknowledges the byte received from the array address 7FFF. CURRENT ADDRESS READ BUS ACTIVITY MASTER Random Read N O A C K RANDOM READ S T A R T CONTROL BYTE ADDRESS HIGH BYTE S1 0 1 0 AAA0 210 X A C K A C K BUS ACTIVITY S T A R T ADDRESS LOW BYTE A C K CONTROL BYTE S 1 0 1 0 A A A1 210 S T O P DATA BYTE P N O A C K A C K X = Don’t Care Bit FIGURE 8-3: BUS ACTIVITY MASTER SEQUENTIAL READ CONTROL BYTE DATA (n) DATA (n + 1) S T O P DATA (n + X) DATA (n + 2) P SDA LINE BUS ACTIVITY DS21203J-page 10 A C K A C K Preliminary A C K A C K N O A C K 2002 Microchip Technology Inc. 24AA256/24LC256/24FC256 9.0 PACKAGING INFORMATION 9.1 Package Marking Information 8-Lead PDIP (300 mil) Example: 24AA256 I/P017 0110 XXXXXXXX XXXXXNNN YYWW 8-Lead SOIC (150 mil) Example: XXXXXXXX XXXXYYWW NNN 24LC256 I/SN0110 017 8-Lead SOIC (208 mil) Example: XXXXXXXX XXXXXXXX YYWWNNN 24LC256 I/SM 0110017 Example: 8-Lead TSSOP XXXX XYWW NNN Legend: Note: * XX...X Y YY WW NNN 4LD I101 017 Customer specific information* Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week ‘01’) Alphanumeric traceability code In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line thus limiting the number of available characters for customer specific information. Standard device marking consists of Microchip part number, year code, week code, and traceability code. For device marking beyond this, certain price adders apply. Please check with your Microchip Sales Office. 2002 Microchip Technology Inc. Preliminary DS21203J-page 11 24AA256/24LC256/24FC256 Package Marking Information (Continued) 8-Lead MSOP Example: XXXXXX 4L256I YWWNNN 101017 Example : 8-Lead DFN XXXXXXXX XXXXXXXX YYWWNNN 24LC256 XXXXXXXX 0110017 14-Lead TSSOP Example : 24LC256I 0110 017 XXXXXXXX YYWW NNN Legend: Note: * XX...X Y YY WW NNN Customer specific information* Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week ‘01’) Alphanumeric traceability code In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line thus limiting the number of available characters for customer specific information. Standard device marking consists of Microchip part number, year code, week code, and traceability code. For device marking beyond this, certain price adders apply. Please check with your Microchip Sales Office. DS21203J-page 12 Preliminary 2002 Microchip Technology Inc. 24AA256/24LC256/24FC256 8-Lead Plastic Dual In-line (P) – 300 mil (PDIP) E1 D 2 n 1 α E A2 A L c A1 β B1 p eB B Units Dimension Limits n p Number of Pins Pitch Top to Seating Plane Molded Package Thickness Base to Seating Plane Shoulder to Shoulder Width Molded Package Width Overall Length Tip to Seating Plane Lead Thickness Upper Lead Width Lower Lead Width Overall Row Spacing Mold Draft Angle Top Mold Draft Angle Bottom * Controlling Parameter § Significant Characteristic § A A2 A1 E E1 D L c B1 B eB α β MIN .140 .115 .015 .300 .240 .360 .125 .008 .045 .014 .310 5 5 INCHES* NOM MAX 8 .100 .155 .130 .170 .145 .313 .250 .373 .130 .012 .058 .018 .370 10 10 .325 .260 .385 .135 .015 .070 .022 .430 15 15 MILLIMETERS NOM 8 2.54 3.56 3.94 2.92 3.30 0.38 7.62 7.94 6.10 6.35 9.14 9.46 3.18 3.30 0.20 0.29 1.14 1.46 0.36 0.46 7.87 9.40 5 10 5 10 MIN MAX 4.32 3.68 8.26 6.60 9.78 3.43 0.38 1.78 0.56 10.92 15 15 Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side. JEDEC Equivalent: MS-001 Drawing No. C04-018 2002 Microchip Technology Inc. Preliminary DS21203J-page 13 24AA256/24LC256/24FC256 8-Lead Plastic Small Outline (SN) – Narrow, 150 mil (SOIC) E E1 p D 2 B n 1 h α 45× c A2 A f β L Units Dimension Limits n p Number of Pins Pitch Overall Height Molded Package Thickness Standoff § Overall Width Molded Package Width Overall Length Chamfer Distance Foot Length Foot Angle Lead Thickness Lead Width Mold Draft Angle Top Mold Draft Angle Bottom * Controlling Parameter § Significant Characteristic A A2 A1 E E1 D h L f c B α β MIN .053 .052 .004 .228 .146 .189 .010 .019 0 .008 .013 0 0 A1 INCHES* NOM 8 .050 .061 .056 .007 .237 .154 .193 .015 .025 4 .009 .017 12 12 MAX .069 .061 .010 .244 .157 .197 .020 .030 8 .010 .020 15 15 MILLIMETERS NOM 8 1.27 1.35 1.55 1.32 1.42 0.10 0.18 5.79 6.02 3.71 3.91 4.80 4.90 0.25 0.38 0.48 0.62 0 4 0.20 0.23 0.33 0.42 0 12 0 12 MIN MAX 1.75 1.55 0.25 6.20 3.99 5.00 0.51 0.76 8 0.25 0.51 15 15 Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side. JEDEC Equivalent: MS-012 Drawing No. C04-057 DS21203J-page 14 Preliminary 2002 Microchip Technology Inc. 24AA256/24LC256/24FC256 8-Lead Plastic Small Outline (SM) – Medium, 208 mil (SOIC) E E1 p D 2 n 1 B α c A2 A f L β Units Dimension Limits n p Number of Pins Pitch Overall Height Molded Package Thickness Standoff § Overall Width Molded Package Width Overall Length Foot Length Foot Angle Lead Thickness Lead Width Mold Draft Angle Top Mold Draft Angle Bottom * Controlling Parameter § Significant Characteristic A A2 A1 E E1 D L f c B α β MIN .070 .069 .002 .300 .201 .202 .020 0 .008 .014 0 0 INCHES* NOM 8 .050 .075 .074 .005 .313 .208 .205 .025 4 .009 .017 12 12 A1 MAX .080 .078 .010 .325 .212 .210 .030 8 .010 .020 15 15 MILLIMETERS NOM 8 1.27 1.78 1.97 1.75 1.88 0.05 0.13 7.62 7.95 5.11 5.28 5.13 5.21 0.51 0.64 0 4 0.20 0.23 0.36 0.43 0 12 0 12 MIN MAX 2.03 1.98 0.25 8.26 5.38 5.33 0.76 8 0.25 0.51 15 15 Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side. Drawing No. C04-056 2002 Microchip Technology Inc. Preliminary DS21203J-page 15 24AA256/24LC256/24FC256 8-Lead Plastic Thin Shrink Small Outline (ST) – 4.4 mm (TSSOP) E E1 p D 2 1 n B α A c φ β A1 A2 L Units Dimension Limits n p Number of Pins Pitch Overall Height Molded Package Thickness Standoff § Overall Width Molded Package Width Molded Package Length Foot Length Foot Angle Lead Thickness Lead Width Mold Draft Angle Top Mold Draft Angle Bottom * Controlling Parameter § Significant Characteristic A A2 A1 E E1 D L φ c B α β MIN INCHES NOM MAX 8 .026 .033 .002 .246 .169 .114 .020 0 .004 .007 0 0 .035 .004 .251 .173 .118 .024 4 .006 .010 5 5 .043 .037 .006 .256 .177 .122 .028 8 .008 .012 10 10 MILLIMETERS* NOM MAX 8 0.65 1.10 0.85 0.90 0.95 0.05 0.10 0.15 6.25 6.38 6.50 4.30 4.40 4.50 2.90 3.00 3.10 0.50 0.60 0.70 0 4 8 0.09 0.15 0.20 0.19 0.25 0.30 0 5 10 0 5 10 MIN Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .005” (0.127mm) per side. JEDEC Equivalent: MO-153 Drawing No. C04-086 DS21203J-page 16 Preliminary 2002 Microchip Technology Inc. 24AA256/24LC256/24FC256 8-Lead Plastic Micro Small Outline Package (MS) (MSOP) E p E1 D 2 B n 1 α A2 A c φ A1 (F) L β Units Number of Pins Pitch Dimension Limits n p Overall Height MILLIMETERS* INCHES MIN MAX NOM 0.65 .044 .030 Standoff A1 .002 E .184 Molded Package Width MAX 8 .026 A A2 Overall Width NOM 8 Molded Package Thickness § MIN .034 1.18 .038 0.76 .006 0.05 .193 .200 0.86 0.97 4.67 4.90 .5.08 0.15 E1 .114 .118 .122 2.90 3.00 3.10 Overall Length D .114 .118 .122 2.90 3.00 3.10 Foot Length L .016 .022 .028 0.40 0.55 0.70 Footprint (Reference) .035 .037 .039 0.90 0.95 1.00 Foot Angle F φ 6 0 Lead Thickness c .004 .006 .008 0.10 0.15 0.20 Lead Width B α .010 .012 .016 0.25 0.30 0.40 Mold Draft Angle Top Mold Draft Angle Bottom β 0 6 7 7 7 7 *Controlling Parameter § Significant Characteristic Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" (0.254mm) per side. Drawing No. C04-111 2002 Microchip Technology Inc. Preliminary DS21203J-page 17 24AA256/24LC256/24FC256 8-Lead Micro Leadframe Package (MF) 6x5 mm Body (DFN-S) (Formerly MLF-S) E p B E1 n L R D1 D 1 D2 PIN 1 ID EXPOSED METAL PADS 2 E2 TOP VIEW BOTTOM VIEW α A2 A3 A A1 INCHES Units Dimension Limits n p Number of Pins Pitch Overall Height Molded Package Thickness Standoff Base Thickness Overall Length Molded Package Length Exposed Pad Length Overall Width A A2 A1 A3 E E1 E2 D Molded Package Width Exposed Pad Width Lead Width Lead Length Tie Bar Width Mold Draft Angle Top D1 D2 B L R α MIN .000 .152 .085 .014 .020 NOM 8 .050 BSC .033 .026 .0004 .008 REF. .194 BSC .184 BSC .158 .236 BSC .226 BSC .091 .016 .024 .014 MILLIMETERS* MAX MIN .039 .031 .002 0.00 .163 3.85 .097 .019 .030 2.16 0.35 0.50 12 NOM 8 1.27 BSC 0.85 0.65 0.01 0.20 REF. 4.92 BSC 4.67 BSC 4.00 5.99 BSC 5.74 BSC 2.31 0.40 0.60 .356 MAX 1.00 0.80 0.05 4.15 2.46 0.47 0.75 12 *Controlling Parameter Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side. JEDEC equivalent: pending Drawing No. C04-113 DS21203J-page 18 Preliminary 2002 Microchip Technology Inc. 24AA256/24LC256/24FC256 8-Lead Micro Leadframe Package (MF) 6x5 mm Body (DFN-S) (Continued) M SOLDER MASK M p B PACKAGE EDGE L Units Pitch Dimension Limits p INCHES MIN NOM MILLIMETERS* MAX MIN .050 BSC NOM MAX 1.27 BSC Pad Width B .014 .016 .019 0.35 0.40 0.47 Pad Length L .020 .024 .030 0.50 0.60 0.75 Pad to Solder Mask M .005 .006 0.13 0.15 *Controlling Parameter Drawing No. C04-2113 2002 Microchip Technology Inc. Preliminary DS21203J-page 19 24AA256/24LC256/24FC256 14-Lead Plastic Thin Shrink Small Outline (ST) – 4.4 mm (TSSOP) E E1 p D 2 1 n B α A c f β A1 L Units Dimension Limits n p Number of Pins Pitch Overall Height Molded Package Thickness Standoff § Overall Width Molded Package Width Molded Package Length Foot Length Foot Angle Lead Thickness Lead Width Mold Draft Angle Top Mold Draft Angle Bottom * Controlling Parameter § Significant Characteristic A A2 A1 E E1 D L f c B α β MIN .033 .002 .246 .169 .193 .020 0 .004 .007 0 0 INCHES NOM 14 .026 .035 .004 .251 .173 .197 .024 4 .006 .010 5 5 A2 MAX .043 .037 .006 .256 .177 .201 .028 8 .008 .012 10 10 MILLIMETERS* NOM MAX 14 0.65 1.10 0.85 0.90 0.95 0.05 0.10 0.15 6.25 6.38 6.50 4.30 4.40 4.50 4.90 5.00 5.10 0.50 0.60 0.70 0 4 8 0.09 0.15 0.20 0.19 0.25 0.30 0 5 10 0 5 10 MIN Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .005” (0.127mm) per side. JEDEC Equivalent: MO-153 Drawing No. C04-087 DS21203J-page 20 Preliminary 2002 Microchip Technology Inc. 24AA256/24LC256/24FC256 ON-LINE SUPPORT Systems Information and Upgrade Hot Line Microchip provides on-line support on the Microchip World Wide Web (WWW) site. The web site is used by Microchip as a means to make files and information easily available to customers. To view the site, the user must have access to the Internet and a web browser, such as Netscape or Microsoft Explorer. Files are also available for FTP download from our FTP site. The Systems Information and Upgrade Line provides system users a listing of the latest versions of all of Microchip's development systems software products. Plus, this line provides information on how customers can receive any currently available upgrade kits.The Hot Line Numbers are: 1-800-755-2345 for U.S. and most of Canada, and 1-480-792-7302 for the rest of the world. Connecting to the Microchip Internet Web Site 013001 T he Microchip web site is available by using your favorite Internet browser to attach to: www.microchip.com The file transfer site is available by using an FTP service to connect to: ftp://ftp.microchip.com The web site and file transfer site provide a variety of services. Users may download files for the latest Development Tools, Data Sheets, Application Notes, User's Guides, Articles and Sample Programs. A variety of Microchip specific business information is also available, including listings of Microchip sales offices, distributors and factory representatives. Other data available for consideration is: • Latest Microchip Press Releases • Technical Support Section with Frequently Asked Questions • Design Tips • Device Errata • Job Postings • Microchip Consultant Program Member Listing • Links to other useful web sites related to Microchip Products • Conferences for products, Development Systems, technical information and more • Listing of seminars and events 2002 Microchip Technology Inc. Preliminary DS21203J-page 21 24AA256/24LC256/24FC256 READER RESPONSE It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150. Please list the following information, and use this outline to provide us with your comments about this Data Sheet. To: Technical Publications Manager RE: Reader Response Total Pages Sent From: Name Company Address City / State / ZIP / Country Telephone: (_______) _________ - _________ FAX: (______) _________ - _________ Application (optional): Would you like a reply? Y N Device: 24AA256/24LC256/24FC256 Literature Number: DS21203J Questions: 1. What are the best features of this document? 2. How does this document meet your hardware and software development needs? 3. Do you find the organization of this data sheet easy to follow? If not, why? 4. What additions to the data sheet do you think would enhance the structure and subject? 5. What deletions from the data sheet could be made without affecting the overall usefulness? 6. Is there any incorrect or misleading information (what and where)? 7. How would you improve this document? 8. How would you improve our software, systems, and silicon products? DS21203J-page 22 Preliminary 2002 Microchip Technology Inc. 24AA256/24LC256/24FC256 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. Device X Examples: /XX Temperature Range a) Package b) c) Device: 24AA256: 24AA256T: 24LC256: 24LC256T: 24FC256: 24FC256T: 256 Kbit 1.8V I2C Serial EEPROM 256 Kbit 1.8V I2C Serial EEPROM (Tape and Reel) 256 Kbit 2.5V I2C Serial EEPROM 256 Kbit 2.5V I2C Serial EEPROM (Tape and Reel) 256 Kbit 1 MHz I2C Serial EEPROM 256 Kbit 1 MHz I2C Serial EEPROM (Tape and Reel) d) a) b) c) d) Temperature Range: Package: I E = = P SN SM ST ST14 MF MS -40°C to +85°C -40°C to +125°C = = = = = = = a) Plastic DIP (300 mil body), 8-lead Plastic SOIC (150 mil body), 8-lead Plastic SOIC (208 mil body), 8-lead Plastic TSSOP (4.4 mm), 8-lead Plastic TSSOP (4.4 mm), 14-lead Dual, Flat, No Lead (DFN)(6x5 mm body), 8-lead Plastic Micro Small Outline (MSOP), 8-lead b) c) 24AA256-I/P: Industrial Temperature, PDIP package. 24AA256T-I/SN: Tape and Reel, Industrial Temp., SOIC package. 24AA256-I/ST: Industrial Temperature, TSSOP package. 24AA256-I/MS: Industrial Temperature, MSOP package. 24LC256-E/P: Extended Temperature, PDIP package. 24LC256-I/SN: Industrial Temperature, SOIC package. 24LC256T-I/SN: Tape and Reel, Industrial Temperature, SOIC package. 24LC256-I/MS: Industrial Temperature, MSOP package. 24FC256-I/P: Industrial Temperature, PDIP package. 24FC256-I/SN: Industrial Temperature, SOIC package. 24FC256T-I/SN: Tape and Reel, Industrial Temperature, SOIC package Sales and Support Data Sheets Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and recommended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following: 1. 2. 3. Your local Microchip sales office The Microchip Corporate Literature Center U.S. FAX: (480) 792-7277 The Microchip Worldwide Site (www.microchip.com) Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using. New Customer Notification System Register on our web site (www.microchip.com/cn) to receive the most current information on our products. 2002 Microchip Technology Inc. Preliminary DS21203J-page23 24AA256/24LC256/24FC256 NOTES: DS21203J-page 24 Preliminary 2002 Microchip Technology Inc. 24AA256/24LC256/24FC256 NOTES: 2002 Microchip Technology Inc. Preliminary DS21203J-page25 24AA256/24LC256/24FC256 NOTES: DS21203J-page 26 Preliminary 2002 Microchip Technology Inc. Information contained in this publication regarding device applications and the like is intended through suggestion only and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. No representation or warranty is given and no liability is assumed by Microchip Technology Incorporated with respect to the accuracy or use of such information, or infringement of patents or other intellectual property rights arising from such use or otherwise. Use of Microchip’s products as critical components in life support systems is not authorized except with express written approval by Microchip. No licenses are conveyed, implicitly or otherwise, under any intellectual property rights. Trademarks The Microchip name and logo, the Microchip logo, FilterLab, KEELOQ, microID, MPLAB, PIC, PICmicro, PICMASTER, PICSTART, PRO MATE, SEEVAL and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. dsPIC, ECONOMONITOR, FanSense, FlexROM, fuzzyLAB, In-Circuit Serial Programming, ICSP, ICEPIC, microPort, Migratable Memory, MPASM, MPLIB, MPLINK, MPSIM, MXDEV, MXLAB, PICC, PICDEM, PICDEM.net, rfPIC, Select Mode and Total Endurance are trademarks of Microchip Technology Incorporated in the U.S.A. Serialized Quick Turn Programming (SQTP) is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. © 2002, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. Microchip received QS-9000 quality system certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona in July 1999 and Mountain View, California in March 2002. The Company’s quality system processes and procedures are QS-9000 compliant for its PICmicro ® 8-bit MCUs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, non-volatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001 certified. 2002 Microchip Technology Inc. DS21203J - page 27 M WORLDWIDE SALES AND SERVICE AMERICAS ASIA/PACIFIC Corporate Office Australia 2355 West Chandler Blvd. Chandler, AZ 85224-6199 Tel: 480-792-7200 Fax: 480-792-7277 Technical Support: 480-792-7627 Web Address: http://www.microchip.com Microchip Technology Australia Pty Ltd Suite 22, 41 Rawson Street Epping 2121, NSW Australia Tel: 61-2-9868-6733 Fax: 61-2-9868-6755 Rocky Mountain China - Beijing 2355 West Chandler Blvd. Chandler, AZ 85224-6199 Tel: 480-792-7966 Fax: 480-792-4338 Microchip Technology Consulting (Shanghai) Co., Ltd., Beijing Liaison Office Unit 915 Bei Hai Wan Tai Bldg. No. 6 Chaoyangmen Beidajie Beijing, 100027, No. China Tel: 86-10-85282100 Fax: 86-10-85282104 Atlanta 500 Sugar Mill Road, Suite 200B Atlanta, GA 30350 Tel: 770-640-0034 Fax: 770-640-0307 Boston 2 Lan Drive, Suite 120 Westford, MA 01886 Tel: 978-692-3848 Fax: 978-692-3821 Chicago 333 Pierce Road, Suite 180 Itasca, IL 60143 Tel: 630-285-0071 Fax: 630-285-0075 Dallas 4570 Westgrove Drive, Suite 160 Addison, TX 75001 Tel: 972-818-7423 Fax: 972-818-2924 Detroit Tri-Atria Office Building 32255 Northwestern Highway, Suite 190 Farmington Hills, MI 48334 Tel: 248-538-2250 Fax: 248-538-2260 Kokomo 2767 S. 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B Far East International Plaza No. 317 Xian Xia Road Shanghai, 200051 Tel: 86-21-6275-5700 Fax: 86-21-6275-5060 China - Shenzhen 150 Motor Parkway, Suite 202 Hauppauge, NY 11788 Tel: 631-273-5305 Fax: 631-273-5335 Microchip Technology Consulting (Shanghai) Co., Ltd., Shenzhen Liaison Office Rm. 1315, 13/F, Shenzhen Kerry Centre, Renminnan Lu Shenzhen 518001, China Tel: 86-755-2350361 Fax: 86-755-2366086 San Jose China - Hong Kong SAR Microchip Technology Inc. 2107 North First Street, Suite 590 San Jose, CA 95131 Tel: 408-436-7950 Fax: 408-436-7955 Microchip Technology Hongkong Ltd. Unit 901-6, Tower 2, Metroplaza 223 Hing Fong Road Kwai Fong, N.T., Hong Kong Tel: 852-2401-1200 Fax: 852-2401-3431 New York Toronto 6285 Northam Drive, Suite 108 Mississauga, Ontario L4V 1X5, Canada Tel: 905-673-0699 Fax: 905-673-6509 India Microchip Technology Inc. India Liaison Office Divyasree Chambers 1 Floor, Wing A (A3/A4) No. 11, O’Shaugnessey Road Bangalore, 560 025, India Tel: 91-80-2290061 Fax: 91-80-2290062 Japan Microchip Technology Japan K.K. Benex S-1 6F 3-18-20, Shinyokohama Kohoku-Ku, Yokohama-shi Kanagawa, 222-0033, Japan Tel: 81-45-471- 6166 Fax: 81-45-471-6122 Korea Microchip Technology Korea 168-1, Youngbo Bldg. 3 Floor Samsung-Dong, Kangnam-Ku Seoul, Korea 135-882 Tel: 82-2-554-7200 Fax: 82-2-558-5934 Singapore Microchip Technology Singapore Pte Ltd. 200 Middle Road #07-02 Prime Centre Singapore, 188980 Tel: 65-6334-8870 Fax: 65-6334-8850 Taiwan Microchip Technology (Barbados) Inc., Taiwan Branch 11F-3, No. 207 Tung Hua North Road Taipei, 105, Taiwan Tel: 886-2-2717-7175 Fax: 886-2-2545-0139 EUROPE Denmark Microchip Technology Nordic ApS Regus Business Centre Lautrup hoj 1-3 Ballerup DK-2750 Denmark Tel: 45 4420 9895 Fax: 45 4420 9910 France Microchip Technology SARL Parc d’Activite du Moulin de Massy 43 Rue du Saule Trapu Batiment A - ler Etage 91300 Massy, France Tel: 33-1-69-53-63-20 Fax: 33-1-69-30-90-79 Germany Microchip Technology GmbH Gustav-Heinemann Ring 125 D-81739 Munich, Germany Tel: 49-89-627-144 0 Fax: 49-89-627-144-44 Italy Microchip Technology SRL Centro Direzionale Colleoni Palazzo Taurus 1 V. Le Colleoni 1 20041 Agrate Brianza Milan, Italy Tel: 39-039-65791-1 Fax: 39-039-6899883 United Kingdom Microchip Ltd. 505 Eskdale Road Winnersh Triangle Wokingham Berkshire, England RG41 5TU Tel: 44 118 921 5869 Fax: 44-118 921-5820 Austria Microchip Technology Austria GmbH Durisolstrasse 2 A-4600 Wels Austria Tel: 43-7242-2244-399 Fax: 43-7242-2244-393 05/16/02 DS21203J-page 28 2002 Microchip Technology Inc. ...
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