AT91R40807 Electrical Characteristics

AT91R40807 Electrical Characteristics - Features •...

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Unformatted text preview: Features • Incorporates the ARM7TDMI™ ARM® Thumb® Processor Core • • • • • • • • • • • – High-performance 32-bit RISC Architecture – High-density 16-bit Instruction Set – Leader in MIPS/Watt – Embedded ICE (In-Circuit Emulation) 136K Bytes of On-chip SRAM – 32-bit Data Bus – Single-clock Cycle Access Fully-programmable External Bus Interface (EBI) – Maximum External Address Space of 64M Bytes – Up to Eight Chip Selects – Software Programmable 8-/16-bit External Data Bus 8-level Priority, Individually Maskable, Vectored Interrupt Controller – Four External Interrupts, Including a High-priority Low-latency Interrupt Request 32 Programmable I/O Lines Three-channel 16-bit Timer/Counter – Three External Clock Inputs – Two Multi-purpose I/O Pins per Channel Two USARTs – Two Dedicated Peripheral Data Controller (PDC) Channels per USART Programmable Watchdog Timer Advanced Power-saving Features – CPU and Peripherals Can be Deactivated Individually Fully Static Operation: 0 Hz to 33 MHz Internal Frequency Range at 3.0 V, 85°C 1.8V to 3.6V Operating Range Available in a 100-lead TQFP Package AT91 ARM® Thumb® Microcontroller s AT91R40807 Electrical Characteristics Description The AT91R40807 microcontroller is a member of the Atmel AT91 16-/32-bit microcontroller family, which is based on the ARM7TDMI processor core. This processor has a high-performance 32-bit RISC architecture with a high-density 16-bit instruction set and very low power consumption. In addition, a large number of internally banked registers result in very fast exception handling, making the device ideal for real-time control applications. The AT91R40807 microcontroller features a direct connection to off-chip memory, including Flash, through the fully-programmable External Bus Interface (EBI). An eight-level priority vectored interrupt controller, in conjunction with the Peripheral Data Controller, significantly improves the real-time performance of the device. The device is manufactured using Atmel’s high-density CMOS technology. By combining the ARM7TDMI processor core with a large on-chip high-speed SRAM and a wide range of peripheral functions on a monolithic chip, the AT91R40807 is a powerful microcontroller that offers a flexible and high-performance solution to many computeintensive embedded control applications. Rev. 1367C–01/02 1 Absolute Maximum Ratings* Operating Temperature (Industrial) ....-40°C to + 85°C *NOTICE: Storage Temperature........................-60°C to + 150°C Voltage on Any Input Pin with Respect to Ground......................-0.5V to + 3.9V Maximum Operating Voltage ................................4.6V Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. DC Output Current ..............................................6 mA DC Characteristics The following characteristics are applicable to the Operating Temperature range: TA = -40°C to +85°C, unless otherwise specified and are certified for a Junction Temperature up to TJ = 100°C. Table 1. DC Characteristics Symbol Parameter VDD DC Supply VIL Input Low Voltage VIH Conditions Max Units 1.8 3.6 V VDD = 3.0V to 3.6V -0.3 0.3 x VDD V Input High Voltage VDD= 3.0V to 3.6V 0.7 x VDD VDD + 0.3 V VOL Output Low Voltage IOL = 0.3 mA, VDD = 3.0V 0.1 V VOH Output High Voltage IOH = 0.3 mA, VDD = 3.0V ILEAK Input Leakage Current IPULL Input Pull-up Current CIN Input Capacitance 2 Typ VDD - 0.1 V 390 µA 6.8 TA = 25°C nA 350 VDD = 3.6V, VIN = 0V VDD = 3.6V; MCKI = 0 Hz ISC Min pF 45 Static Current µA All inputs driven TMS, TDI, TCK, NRST = 1 TA = 85°C 900 AT91R40807 1367C–01/02 AT91R40807 Power Consumption The values in the following tables are measured values in the operating conditions indicated (i.e., VDD = 3.3V or 2.0V, TA = 25°C) on the AT91EB40 Evaluation Board. Table 2. Power Consumption VDD 2.0V 3.3V 0.08 0.20 Fetch in ARM mode out of internal SRAM All peripheral clocks activated 1.56 5.34 Fetch in ARM mode out of internal SRAM All peripheral clocks deactivated 1.39 4.64 All peripheral clocks activated 0.41 1.34 All peripheral clocks deactivated Mode 0.14 1.00 Conditions Reset Units Normal mW/MHz Idle Table 3. Power Consumption per Peripheral VDD Peripheral 2.0V 3.3V PIO Controller 0.03 0.12 Timer/Counter Channel 0.02 0.10 Timer/Counter Block (3 Channels) 0.06 0.31 USART 0.04 Units 0.18 mW/MHz 3 1367C–01/02 Thermal and Reliability Considerations Thermal Data In Table 4, the device lifetime is estimated with the MIL-217 standard in the “moderately controlled” environmental model (this model is described as corresponding to an installation in a permanent rack with adequate cooling air), depending on the device Junction Temperature. (For details see the section “Junction Temperature” on page 5.) Note that the user must be extremely cautious with this MTBF calculation: as the MIL-217 model is pessimistic with respect to observed values due to the way the data/models are obtained (test under severe conditions). The life test results that have been measured are always better than the predicted ones. Table 4. MTBF Versus Junction Temperature Junction Temperature (TJ) (°C) Estimated Lifetime (MTBF) (Year) 100 13 125 7 150 4 175 2 Table 5 summarizes the thermal resistance data related to the package of interest Table 5. Thermal Resistance Data Symbol θJA= Junction-to-ambient thermal resistance θJC Reliability Data Parameter Condition Package Typ Still Air TQFP100 Junction-to-case thermal resistance 40 TQFP100 Units 6.4 °C/W The number of gates and the device die size are provided for the user to calculate reliability data with another standard and/or in another environmental model. Table 6. Reliability Data Parameter Unit Number of Logic Gates 272 K gates Number of Memory Gates 7,006 K gates Device Die Size 4 Data 59.8 mm2 AT91R40807 1367C–01/02 AT91R40807 Junction Temperature The average chip-junction temperature TJ in °C can be obtained from the following: 1. T J = T A + ( P D × θ JA ) 2. T J = T A + ( P D × ( θ HEATSINK + θ JC ) ) Where: • θJA = package thermal resistance, Junction-to-ambient (°C/W), provided in Table 5 on page 4. • θJC = package thermal resistance, Junction-to-case thermal resistance (°C/W), provided in Table 5 on page 4. • θHEAT SINK = cooling device thermal resistance (°C/W), provided in the device datasheet. • PD = device power consumption (W) estimated from data provided in the section “Power Consumption” on page 3. • TA = ambient temperature (°C). From the first equation, the user can derive the estimated lifetime of the chip and thereby decide if a cooling device is necessary or not. If a cooling device is to be fitted on the chip, the second equation should be used to compute the resulting average chip-junction temperature TJ in °C. 5 1367C–01/02 Conditions Timing Results The delays are given as typical values in the following conditions: • VDD = 3.3V • Ambient Temperature = 25°C • Load Capacitance is 0 pF • The output level change detection is (0.5 x VDD). • The input level is (0.3 x VDD) for a low-level detection and is (0.7 x VDD) for a high level detection. The minimum and maximum values given in the AC characteristics tables of this datasheet take into account the process variation and the design. In order to obtain the timing for other conditions, the following equation should be used: t = δ T ° × δ VDD × ( t DATASHEET + ( C SIGNAL × δ CSIGNAL ) ) where • δT° is the derating factor in temperature given in the Figure 1 on page 7. • δVDD is the derating factor for the Power Supply given in Figure 2 on page 7. • tdatasheet is the minimum or maximum timing value given in this datasheet for a load capacitance of 0 pF. • CSignal is the capacitance load on the considered output pin.(1) • δCSignal is the load derating factor depending on the capacitance load on the related output pins given in Min and Max in this datasheet. The input delays are given as typical value. Note: 6 1. The user must take into account the package capacitance load contribution (CIN) described in Table 1 on page 2. AT91R40807 1367C–01/02 AT91R40807 Temperature Derating Factor Figure 1. Derating Curve for Different Operating Temperatures 1.3 Derating Factor 1.2 1.1 Derating Factor for Typ Case is 1 1 0.9 0.8 -60 -40 -20 0 20 40 60 80 100 120 140 160 180 Operating Temperature (°C) Figure 2. Derating Curve for Different Supply Voltages Derating Factor Voltage Derating Factor 1.70 1.65 1.60 1.55 1.50 1.45 1.40 1.35 1.30 1.25 1.20 1.15 1.10 1.05 1.00 0.95 0.90 Derating Factor for Typ Case is 1 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 Supply Voltage (V) Note: This derating factor is applicable only to timings related to output pins. 7 1367C–01/02 Clock Waveforms Table 7. Clock Waveform Parameters Symbol Parameter Conditions Min Max Units 1/(tCP) Oscillator Frequency 42.6 MHz tCP Oscillator Period 23.5 tCH High Half-period 0.45 x tCP 0.55 x tCP tCL Low Half-period 0.45 x tCP 0.55 x tCP tr Rising Edge TBD tf Falling Edge TBD ns Table 8. Clock Propagation Times Symbol Parameter Conditions tCDLH Rising Edge Propagation Time tCDHL Falling Edge Propagation Time Min Max Units CMCKO = 0 pF 4.6 7.2 ns 0.032 0.05 ns/pF 5.8 9.0 ns 0.032 0.05 ns/pF CMCKO derating CMCKO = 0 pF CMCKO derating Figure 3. Clock Waveform tr tCH 0.7 VDD tf 0.3 VDD MCKI tCL tCP 0.5 VDD MCKO tCDLH 8 0.5 VDD tCDHL AT91R40807 1367C–01/02 AT91R40807 Table 9. NRST to MCKO Symbol Parameter Min tD NRST Rising Edge to MCKO Valid Time Max Units 3(tCP/2) 7(tCP/2) ns Figure 4. MCKO Relative to NRST NRST tD MCKO 9 1367C–01/02 AC Characteristics EBI Signals Relative to MCKI The following tables show timings relative to operating condition limits defined in in the section “Conditions” on page 6. See Figure 5 on page 14. Table 10. General-purpose EBI Signals Symbol Parameter EBI1 MCKI Falling to NUB Valid EBI2 MCKI Falling to NLB/A0 Valid EBI3 MCKI Falling to A1 - A23 Valid EBI4 MCKI Falling to Chip Select Change EBI5 NWAIT Setup before MCKI Rising 0.5 ns EBI6 NWAIT Hold after MCKI Rising 3.0 ns 10 Conditions Min Max Units CNUB = 0 pF 5.9 11.6 ns 0.032 0.05 ns/pF 5.2 8.8 ns 0.032 0.05 ns/pF 4.7 9.9 ns 0.032 0.05 ns/pF 5.3 10.8 ns 0.032 0.05 ns/pF CNUB derating CNLB = 0 pF CNLB derating CADD = 0 pF CADD derating CNCS = 0 pF CNCS derating AT91R40807 1367C–01/02 AT91R40807 Table 11. EBI Write Signals Symbol Parameter EBI7 MCKI Rising to NWR Active (No Wait States) EBI8 MCKI Rising to NWR Active (Wait States) EBI9 MCKI Falling to NWR Inactive (No Wait States) EBI10 MCKI Rising to NWR Inactive (Wait States) EBI11 MCKI Rising to D0 - D15 Out Valid EBI12 NWR High to NUB Change EBI13 NWR High to NLB/A0 Change EBI14 NWR High to A1 - A23 Change EBI15 NWR High to Chip Select Inactive EBI16 Data Out Valid before NWR High (No Wait States) (1) Conditions Min Max Units CNWR = 0 pF 4.3 7.5 ns 0.032 0.05 ns/pF 4.9 8.5 ns 0.032 0.05 ns/pF 5.1 8.8 ns 0.032 0.049 ns/pF 4.6 8.0 ns 0.032 0.049 ns/pF 4.0 9.1 ns 0 0.051 ns/pF 3.3 7.2 ns 0.031 0.05 ns/pF 3.2 5.6 ns 0.032 0.05 ns/pF 2.7 7.1 ns 0.032 0.05 ns/pF 3.0 6.8 ns 0.031 0.05 ns/pF CNWR derating CNWR = 0 pF CNWR derating CNWR = 0 pF CNWR derating CNWR = 0 pF CNWR derating CDATA = 0 pF CDATA derating CNUB = 0 pF CNUB derating CNLB = 0 pF CNLB derating CADD = 0 pF CADD derating CNCS = 0 pF CNCS derating C = 0 pF tCH - 1.1 ns CDATA derating -0.051 ns/pF CNWR derating 0.049 ns/pF n x tCP - 1.9 (2) ns CDATA derating -0.051 ns/pF CNWR derating 0.049 ns/pF 2.1 ns tCH + 0.4 ns n x tCP - 1.2 (2) ns C = 0 pF Data Out Valid before NWR High (Wait States) (1) EBI17 EBI18 Data Out Valid after NWR High EBI19 NWR Minimum Pulse Width (No Wait States) (1) EBI20 NWR Minimum Pulse Width (Wait States) (1) Notes: 1. The derating factor is not to be applied to tCH or tCP.. 2. n = number of wait states inserted. 11 1367C–01/02 Table 12. EBI Read Signals Symbol Parameter Conditions EBI21 MCKI Falling to NRD Active (1) EBI22 MCKI Rising to NRD Active (2) EBI23 MCKI Falling to NRD Inactive (1) EBI24 MCKI Falling to NRD Inactive (2) EBI25 Min Max Units CNRD = 0 pF 5.5 9.6 ns 0.032 0.05 ns/pF 4.1 8.5 ns 0.032 0.05 ns/pF 5.5 8.8 ns 0.031 0.049 ns/pF 5.1 8.0 ns 0.031 0.049 ns/pF D0 - D15 in Setup Before MCKI Falling (5) CNRD derating CNRD = 0 pF CNRD derating CNRD = 0 pF CNRD derating CNRD = 0 pF CNRD derating EBI26 D0 - D15 in Hold After MCKI Falling EBI27 NRD High to NUB Change EBI28 NRD High to NLB/A0 Change EBI29 NRD High to A1 - A23 Change EBI30 NRD High to Chip Select Inactive EBI31 Data Setup Before NRD High (5) EBI32 -1.2 Data Hold After NRD High (5) CNUB = 0 pF CNUB derating CNLB = 0 pF CNLB derating CADD = 0 pF CADD derating CNCS = 0 pF CNCS derating CNRD = 0 pF CNRD derating CNRD = 0 pF CNRD derating CNRD = 0 pF EBI33 NRD Minimum Pulse Width (1, 3) CNRD derating CNRD = 0 pF EBI34 NRD Minimum Pulse Width (2, 3) CNRD derating Notes: 12 1. 2. 3. 4. 5. ns 3.5 (5) ns 3.6 7.3 ns 0.031 0.05 ns/pF 3.2 5.1 ns 0.032 0.05 ns/pF 2.8 6.5 ns 0.032 0.049 ns/pF 3.0 6.2 ns 0.031 0.049 ns/pF 6.9 ns 0.048 ns/pF -2.9 ns -0.031 ns/pF (n + 1) x tCP - 1.1(4) ns -0.001 ns/pF n x tCP + (tCH - 0.5)(4) ns -0.001 ns/pF Early Read Protocol. Standard Read Protocol. The derating factor is not to be applied to tCH or tCP.. n = number of standard wait states. Only one of these two timings needs to be met. AT91R40807 1367C–01/02 AT91R40807 Table 13. EBI Read and Write Control Signals. Capacitance Limitation Symbol Parameter TCPLNRD(1) Master Clock Low Due to NRD Capacitance TCPLNWR(2) Master CLock Low Due to NWR Capacitance Notes: Conditions Min CNRD = 0 pF 9.2 ns CNRD derating 0.048 ns/pF CNWR = 0 pF 9.6 ns 0.049 ns/pF CNWR derating Max Units 1. If this condition is not met, the action depends on the read protocol intended for use. • Early Read Protocol: Programing an additional tDF (Data Float Output Time) cycle. • Standard Read Protocol: Programming an additional tDF Cycle and an additional wait state. 2. Applicable only for chip select programmed with 0 wait state. If this condition is not met, at least one wait state must be programmed. 13 1367C–01/02 Figure 5. EBI Signals Relative to MCKI MCKI EBI4 EBI4 NCS CS EBI3 A1 - A23 EBI5 EBI6 NWAIT EBI1/EBI2 NUB/NLB/A0 EBI21 EBI23 EBI27-30 EBI33 NRD(1) EBI24 EBI22 EBI34 NRD(2) EBI32 EBI31 EBI25 EBI26 D0 - D15 Read EBI9 EBI7 EBI12-15 EBI19 NWR (No Wait States) EBI8 EBI10 EBI20 NWR (Wait States) EBI17 EBI11 EBI16 EBI18 EBI18 D0 - D15 to Write No Wait Notes: 14 Wait 1. Early Read Protocol. 2. Standard Read Protocol. AT91R40807 1367C–01/02 AT91R40807 Peripheral Signals USART Signals The inputs must meet the minimum pulse width and period constraints shown in Table 14 and Table 15, and represented in Figure 6. Table 14. USART Asynchronous Mode Input Minimum Pulse Width Symbol Parameter Min Pulse Width US1 SCK/RXD Minimum Pulse Width Units 5(tCP/2) ns Min Input Period Units 9(tCP/2) ns Table 15. USART Minimum Input Period Symbol Parameter US2 SCK Minimum Input Period Figure 6. USART Signals US1 RXD US2 US1 SCK 15 1367C–01/02 Timer/Counter Signals Due to internal synchronization of input signals, there is a delay between an input event and a corresponding output event. This delay is 3(tCP) in Waveform Event Detection mode and 4(tCP) in Waveform Total-count Detection mode. The inputs have to meet the minimum pulse width and minimum input period shown in Tables 16 and 17 and as represented in Figure 7. Table 16. Timer Input Minimum Pulse Width Symbol Parameter Min Pulse Width TC1 TCLK/TIOA/TIOB Minimum Pulse Width Units 3(tCP/2) ns Min Input Period Units 5(tCP/2) ns Table 17. Timer Input Minimum Period Symbol Parameter TC2 TCLK/TIOA/TIOB Minimum Input Period Figure 7. Timer Input TC2 3(tCP/2) 3(tCP/2) MCKI TC1 TIOA/TIOB/TCLK Reset Signals A minimum pulse width is necessary as shown in Table 18 and as represented in Figure 8. Table 18. Reset Minimum Pulse Width Symbol Parameter RST1 Min Pulse Width NRST Minimum Pulse Width Units 10(tCP) ns Figure 8. Reset Signal RST1 NRST Only the NRST rising edge is synchronized with MCKI. The falling edge is asynchronous. 16 AT91R40807 1367C–01/02 AT91R40807 Advanced Interrupt Controller Signals Inputs must meet the minimum pulse width and mimimum input period shown in Table 19 and Table 20 and represented in Figure 9. Table 19. AIC Input Minimum Pulse Width Symbol Parameter AIC1 Min Pulse Width FIQ/IRQ0/IRQ1/IRQ2/IRQ3 Minimum Pulse Width Unit 3(tCP/2) ns Min Input Period Unit 5(tCP/2) ns Table 20. AIC Input Minimum Period Symbol Parameter AIC2 AIC Minimum Input Period Figure 9. AIC Signals AIC2 MCKI AIC1 FIQ/IRQ0/IRQ1/IRQ2/IRQ3 Input Parallel I/O Signals The inputs must meet the minimum pulse width shown in Table 21 and as represented in Figure 10. Table 21. PIO Input Minimum Pulse Width Symbol Parameter PIO1 Min Pulse Width PIO Input Minimum Pulse Width Units 3(tCP/2) ns Figure 10. PIO Signal PIO1 PIO Inputs 17 1367C–01/02 ICE Interface Signals Table 22. ICE Interface Timing Specifications Symbol Parameter Conditions Min ICE0 NTRST Minimum Pulse width 18.8 ICE1 NTRST High Recovery to TCK High 1.3 ICE2 NTRST High Removal from TCK High -0.3 ICE3 TCK Low Half-period 41.7 ICE4 TCK High Half-period 40.9 ICE5 TCK Period 82.5 ICE6 TDI, TMS Setup Before TCK High 0.5 ICE7 TDI, TMS Hold After TCK High 0.6 ICE8 TDO Hold Time 5.0 ICE9 TCK Low to TDO Valid Max Units ns CTDO = 0 pF 10.0 CTDO derating 0.05 ns/pF Figure 11. ICE Interface Signals ICE0 NTRST ICE1 ICE2 ICE5 TCK ICE3 ICE4 TMS/TDI ICE6 ICE7 TDO ICE8 ICE9 18 AT91R40807 1367C–01/02 AT91R40807 Document Details Title AT91R40807 Electrical Characteristics Literature Number Lit# 1367C Revision History Version A Publication Date: Apr, 2000 Version B Publication Date: Nov, 2000 Version C Publication Date: 10, Dec, 2001 Revisions Since Previous Version published on Intranet Page: 1 “Features” “Fully Static Operation: 0 Hz to 33 MHz Internal Frequency Range at 3.0 V, 85°C” ..... frequency and range modified Page: 4 “Reliability Data” paragraph modified and new table inserted. “Table 6 Reliability Data” Page: 6 “Timing Results” Cross reference added to CSIGNAL part of equation. Page: 8 Table 7. Master Clock Waveform Parameters. Values have been changed for Oscillator Frequency and Oscillator Period. Some master clock parameters deleted. Page: 10 Table 10. General-purpose EBI Signals. EBI4, Conditions are changed. Page: 13 New table inserted. Table 13. Read and Write Control Signals. Capacitance Limitation. This table adds understanding to EBI Signals Relative to MCK. 19 1367C–01/02 Atmel Headquarters Atmel Operations Corporate Headquarters Memory 2325 Orchard Parkway San Jose, CA 95131 TEL 1(408) 441-0311 FAX 1(408) 487-2600 Europe Atmel SarL Route des Arsenaux 41 Casa Postale 80 CH-1705 Fribourg Switzerland TEL (41) 26-426-5555 FAX (41) 26-426-5500 Asia Atmel Asia, Ltd. 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The Company assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Atmel are granted Atmel ® i s the registered trademark of Atmel. ARM ®, Thumb ® a nd ARM Powered ® a re registered trademarks of ARM Ltd; ARM7TDMI™ i s a trademark of ARM Ltd. Other terms and product names may be the trademarks of others. Printed on recycled paper. 1367C–01/02/0M ...
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This note was uploaded on 01/15/2012 for the course AAE 490 taught by Professor Andrisani during the Fall '09 term at Purdue University.

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