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Unformatted text preview: Problem Set 1 Prof. Luke Theogarajan ECE 194BB/594BB Department of Electrical & Computer Engineering, University of California, Santa Barbara Due October 5 @ 2 p.m., 2010 For all problems, we are using the 0.18 μ m technology node that was intro- duced to you in the CADENCE help section. The maximum supply voltage for this technology is V dd ( Max ) = 1.8 V For hand calculation you may use the following parameters NMOS: V tn = 0 . 5 V,v sat = 1 . 6 × 10 5 m/s,t ox = 41 × 10- 10 m,E sat = 6 × 10 4 V/cm,C ox = 8 . 57 fF/μm 2 ,μ = 412 cm 2 /V sec PMOS: V tp =- . 5 V,v sat = 1 . × 10 5 m/s,t ox = 41 × 10- 10 m,E sat = 24 × 10 4 V/cm,C ox = 8 . 57 fF/μm 2 ,μ = 83 cm 2 /V sec You may find the following equation useful V DSsat = ( V GS- V t ) E sat L ( V GS- V t )+ E sat L Problem 1 Consider a CMOS process with the following capacitive param- eters for the NMOS transistor: CGSO, CGDO, COX, CJ, mj, Cjsw, mjsw, and PB, with the lateral diffusion equal to LD. The MOS transistor M1 is characterized by the following parameters: W, L, AD, PD, AS, PS.characterized by the following parameters: W, L, AD, PD, AS, PS....
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- Fall '11
- mos transistor, drain capacitance, total input capacitance, linear capacitance CT