ProblemSet_4

# ProblemSet_4 - University of California, Santa Barbara...

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University of California, Santa Barbara High-Performance Digital Circuit Design Professor Theogarajan Due, November 7, 2011 Name: For all questions make reasonable approximations. Unless otherwise speciﬁed ignore body eﬀect. All necessary formulas and values are given at the end of the exam for your conve- nience. GOOD LUCK! Answer the questions in the spaces provided on the question sheets. If you run out of room for an answer, continue on the back of the page. Question Points Score 1 20 2 20 3 20 4 20 5 20 Total: 100

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ECE 123/223 Problemset 4 November 1, 2011 1. Question 1: 20points Consider the logic path shown in ﬁgure 1 Figure 1: Question 1 (a) (10 points) Size the gates for the minimum possible delay and calculate the path delay given that an inverter with an fan-out of 4 has a delay of 60ps.
(Problemset 4 Continued) November 1, 2011 (b) (10 points) Is it possible to decrease the overall path delay by introducing inverters in the path? If yes, add the minimal amount of inverters and recalculate the path delay. Page 2 of 12

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## This note was uploaded on 01/16/2012 for the course ECE 223 taught by Professor Luketheogarajan during the Fall '11 term at UCSB.

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ProblemSet_4 - University of California, Santa Barbara...

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