lect8 - CMOS VLSI For Computer Engineering Lecture 7:...

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Unformatted text preview: CMOS VLSI For Computer Engineering Lecture 7: Sequential Circuits From http://www3.hmc.edu/~harris/cmosvlsi/ 4e/index.html 1 Lecture 7 CMOS VLSI for Computer Engineering Outline Sequencing Sequencing Element Design Max and Min-Delay Clock Skew Time Borrowing Two-Phase Clocking Lecture 7 2 CMOS VLSI for Computer Engineering Sequencing Combinational logic output depends on current inputs Sequential logic output depends on current and previous inputs Requires separating previous, current, future Called state or tokens Ex: FSM, pipeline Lecture 7 3 CL clk in out clk clk clk CL CL Pipeline Finite State Machine CMOS VLSI for Computer Engineering Sequencing Cont. If tokens moved through pipeline at constant speed, no sequencing elements would be necessary Ex: fiber-optic cable Light pulses (tokens) are sent down cable Next pulse sent before first reaches end of cable No need for hardware to separate pulses But dispersion sets min time between pulses This is called wave pipelining in circuits In most circuits, dispersion is high Delay fast tokens so they dont catch slow ones. Lecture 7 4 CMOS VLSI for Computer Engineering Sequencing Overhead Use flip-flops to delay fast tokens so they move through exactly one stage each cycle. Inevitably adds some delay to the slow tokens Makes circuit slower than just the logic delay Called sequencing overhead Some people call this clocking overhead But it applies to asynchronous circuits too Inevitable side effect of maintaining sequence Lecture 7 5 CMOS VLSI for Computer Engineering Sequencing Elements Latch : Level sensitive a.k.a. transparent latch, D latch Flip-flop : edge triggered A.k.a. master-slave flip-flop, D flip-flop, D register Timing Diagrams Transparent Opaque Edge-trigger D Flop Latch Q clk clk D Q clk D Q (latch) Q (flop) Lecture 7 6 D Flop Latch Q clk clk D Q clk D Q (latch) Q (flop) CMOS VLSI for Computer Engineering Latch Design Pass Transistor Latch Pros + Tiny + Low clock load Cons V t drop nonrestoring backdriving output noise sensitivity dynamic diffusion input Lecture 7 7 D Q Used in 1970s CMOS VLSI for Computer Engineering Latch Design Transmission gate + No V t drop- Requires inverted clock Lecture 7 8 D Q CMOS VLSI for Computer Engineering Latch Design Inverting buffer + Restoring + No backdriving + Fixes either Output noise sensitivity Or diffusion input Inverted output Lecture 7 9 D X Q D Q CMOS VLSI for Computer Engineering Latch Design Tristate feedback + Static Backdriving risk Static latches are now essential because of leakage Lecture 7 10 Q D X CMOS VLSI for Computer Engineering Latch Design Buffered input + Fixes diffusion input + Noninverting Lecture 7 11 Q D X CMOS VLSI for Computer Engineering...
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This note was uploaded on 01/16/2012 for the course ECE 223 taught by Professor Luketheogarajan during the Fall '11 term at UCSB.

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lect8 - CMOS VLSI For Computer Engineering Lecture 7:...

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