lect8a

# lect8a - Lecture 6 Combinational Circuit Design From...

This preview shows pages 1–13. Sign up to view the full content.

This preview has intentionally blurred sections. Sign up to view the full version.

View Full Document

This preview has intentionally blurred sections. Sign up to view the full version.

View Full Document

This preview has intentionally blurred sections. Sign up to view the full version.

View Full Document

This preview has intentionally blurred sections. Sign up to view the full version.

View Full Document

This preview has intentionally blurred sections. Sign up to view the full version.

View Full Document

This preview has intentionally blurred sections. Sign up to view the full version.

View Full Document
This is the end of the preview. Sign up to access the rest of the document.

Unformatted text preview: Lecture 6: Combinational Circuit Design From http://www3.hmc.edu/~harris/cmosvlsi/ 4e/index.html CMOS VLSI for Computer Engineering Outline • Bubble Pushing • Compound Gates • Logical Effort Example • Input Ordering • Asymmetric Gates • Skewed Gates • Best P/N ratio 10: Combinational Circuits 2 CMOS VLSI for Computer Engineering Example 1 module mux(input s, d0, d1, output y); assign y = s ? d1 : d0; endmodule 1) Sketch a design using AND, OR, and NOT gates. 10: Combinational Circuits 3 D0 S D1 S Y CMOS VLSI for Computer Engineering Example 2 2) Sketch a design using NAND, NOR, and NOT gates. Assume ~S is available. 10: Combinational Circuits 4 Y D0 S D1 S CMOS VLSI for Computer Engineering Bubble Pushing • Start with network of AND / OR gates • Convert to NAND / NOR + inverters • Push bubbles around to simplify logic Remember DeMorgan’s Law 10: Combinational Circuits 5 Y Y Y D Y (a) (b) (c) (d) CMOS VLSI for Computer Engineering Example 3 3) Sketch a design using one compound gate and one NOT gate. Assume ~S is available. 10: Combinational Circuits 6 Y D0 S D1 S CMOS VLSI for Computer Engineering Compound Gates • Logical Effort of compound gates 10: Combinational Circuits 7 A B C D Y A B C Y A B C C A B A B C D A C B D 2 2 1 4 4 4 2 2 2 2 4 4 4 4 g A = 6/3 g B = 6/3 g C = 5/3 p = 7/3 g A = 6/3 g B = 6/3 g C = 6/3 p = 12/3 g D = 6/3 Y A A Y g A = 3/3 p = 3/3 2 1 Y Y unit inverter AOI21 AOI22 A C D E Y B Y B C A D E A B C D E g A = 5/3 g B = 8/3 g C = 8/3 g D = 8/3 2 2 2 2 2 6 6 6 6 3 p = 16/3 g E = 8/3 Complex AOI Y A B C = + Y A B C D = + ( 29 Y A B C D E = + + Y A = CMOS VLSI for Computer Engineering Example 4 • The multiplexer has a maximum input capacitance of 16 units on each input. It must drive a load of 160 units. Estimate the delay of the two designs. 2 2 4 (4 / 3) (4 / 3) 16 / 9 160/ 9 ˆ 4.2 ˆ 12.4 N P G F GBH f F D Nf P τ = + = = = = = = = = + = g 4 1 5 (6/ 3) (1) 2 20 ˆ 4.5 ˆ 14 N P G F GBH f F D Nf P τ = + = = = = = = = = + = g 10: Combinational Circuits 8 Y D0 S D1 S Y D0 S D1 S H = 160 / 16 = 10 B = 1 N = 2 CMOS VLSI for Computer Engineering Example 5 • Annotate your designs with transistor sizes that achieve this delay. 6 6 6 6 10 10 Y 24 12 10 10 8 8 8 8 8 8 8 8 25 25 25 25 Y 16 16 160 * (4/3) / 4.2 = 50 160 * 1 / 4.5 = 36 10: Combinational Circuits 9 Y 8 8 8 8 8 8 8 8 25 25 25 25 Y 16 160 * (4/3) / 4.2 = 50 Y Y CMOS VLSI for Computer Engineering Input Order • Our parasitic delay model was too simple Calculate parasitic delay for Y falling • If A arrives latest? 2 τ • If B arrives latest? 2.33 τ 10: Combinational Circuits 10 6C 2C 2 2 2 2 B A x Y CMOS VLSI for Computer Engineering Inner & Outer Inputs • Inner input is closest to output (A) • Outer input is closest to rail (B) • If input arrival time is known Connect latest input to inner terminal 10: Combinational Circuits 11 2 2 2 2 A B Y CMOS VLSI for Computer Engineering Asymmetric Gates • Asymmetric gates favor one input over another...
View Full Document

{[ snackBarMessage ]}

### Page1 / 48

lect8a - Lecture 6 Combinational Circuit Design From...

This preview shows document pages 1 - 13. Sign up to view the full document.

View Full Document
Ask a homework question - tutors are online