lecture5

# lecture5 - CMOS VLSI For Computer Engineering Lecture 5 –...

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Unformatted text preview: CMOS VLSI For Computer Engineering Lecture 5 – Logical Effort Prof. Luke Theogarajan parts adapted form Harris – www.cmosvlsi.com and Rabaey- http://bwrc.eecs.berkeley.edu/icbook/sli des.htm CMOS VLSI for Computer Engineering How to optimally size gates to minimize delay • Need a mathematical way of looking at the problem • Consider the following inverter circuit The delay is given by t pd = R eq C int + C ext ( ) C int = C dbn 1 + C dbp 1 C ext = C gsn 2 + C gsp 2 + C wire ≅ 0 for short wires CMOS VLSI for Computer Engineering t pd = R eq C int 1+ C ext C int ae è ç ö ø ÷ C gsp + C gsn C dbn + C dbn = C gate C int = 1 g For any gate define intrinsic input to output capacitance ratio as If we scale the device by S then t pd = R eq S SC int 1+ C ext SC int ae è ç ö ø ÷ = R eq C int 1+ C ext SC int ae è ç ö ø ÷ CMOS VLSI for Computer Engineering Delay as a function of S S Delay So there must be an optimum Delay of driver goes up! CMOS VLSI for Computer Engineering Path delay Need to look at overall path if delay optimization is desired, consider N inverters, The delay of any inverter i is given by: t pdi = R eq C eq 1+ C gate , i +1 C int, i ae è ç ö ø ÷ = R eq C eq 1+ C gate , i +1 gC gate , i ae è ç ç ö ø ÷ ÷ N 1 C L Also C N+1 = C L CMOS VLSI for Computer Engineering Optimal delay ∂ t pd ¶C i = 0 For optimal delay set Collect terms due to C i and differentiate t pd = t p 1+ C i +1 gC i ae è ç ö ø ÷ 1 N å t p = R eq C int Total path delay with C N+1 = C L ∂ ∂ C i C i gC i- 1 + C i +1 gC i ae è ç ö ø ÷ = 0 1 gC i- 1- C i +1 gC i 2 = 0 CMOS VLSI for Computer Engineering Optimal Delay C i = C i +1 C i- 1 Optimal delay occurs when the size is the geometric mean of the neighbors! The above equation can be satisfied when each gate is sized h times its driver since C i +1 C i = C i C i- 1 = h h is called the fanout of the gate CMOS VLSI for Computer Engineering Optimal Delay for a chain of inverters t pd = t p 1+ h g ae è ç ö ø ÷ 1 N å = Nt p 1+ h g ae è ç ö ø ÷ If we want to size purely based on final load then define H = C L C gate 1 h = H N t pd = Nt p 1+ H N g ae è ç ö ø ÷ CMOS VLSI for Computer Engineering 6: Logical Effort 9 How to design any path? • Chip designers face a bewildering array of choices What is the best circuit topology for a function? How many stages of logic give least delay? How wide should the transistors be? • Logical effort is a method to make these decisions Uses a simple model of delay Allows back-of-the-envelope calculations Helps make rapid comparisons between alternatives Emphasizes remarkable symmetries ? ? ? CMOS VLSI for Computer Engineering 6: Logical Effort 10 Example • Ben Bitdiddle is the memory designer for the Motoroil 68W86, an embedded automotive processor. Help Ben design the decoder for a register file....
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lecture5 - CMOS VLSI For Computer Engineering Lecture 5 –...

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